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8839261 Guaranteed core access in a multiple core processing system  
Exclusive access to a core or part of a core, or to multiple cores, but in any case less than all of the cores, of a multiple core processing system. The access can be requested by an instruction,...
8719554 Scaleable status tracking of multiple assist hardware threads  
A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread...
8713290 Scaleable status tracking of multiple assist hardware threads  
A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread...
8407492 System and method of asynchronous logic power management  
Methods, apparatuses, and systems are disclosed to facilitate power management of asynchronous logic devices to operate asynchronous logic devices at a desired level of processing throughput with...
8230431 Guaranteed core access in a multiple core processing system  
Exclusive access to a core or part of a core, or to multiple cores, but in any case less than all of the cores, of a multiple core processing system. The access can be requested by an instruction,...
7721127 Multithreaded dynamic voltage-frequency scaling microprocessor  
A multithreaded microprocessor includes a thread scheduler and voltage-frequency scheduler (VFS). The thread scheduler uses application-specified QoS requirements, which include required...
7707451 Methods and devices for recovering from initialization failures  
The time it takes to recover from a system initialization failure may be reduced by determining whether to enable a recovery process immediately, or defer such a process. Sometimes it is desirable...
7673121 Circuit for monitoring a microprocessor and analysis tool and inputs/outputs thereof  
A method for the transmission of digital messages by the output terminals of a monitoring circuit which is integrated into a microprocessor, the digital messages being representative of first...
7447732 Recoverable return code tracking and notification for autonomic systems  
A system, method and article of manufacture return code management in autonomic systems and more particularly to managing execution of operations in data processing systems on the basis of return...
7401328 Software-implemented grouping techniques for use in a superscalar data processing system  
A data processing system includes a grouping tool coupled to a processor. The grouping tool groups the stream of instructions such that each group of instructions has a dimensionless signature...
7373481 Distributed-structure-based parallel module structure and parallel processing method  
A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1...
7322027 Detecting termination and providing information related to termination of a computer system process  
The present invention extends to mechanisms for detecting termination and providing information related to termination of a computer system process. A computer system loads a termination function...
7302619 Error correction in a cache memory  
Various systems and methods for error correction of instructions in an instruction cache coupled to a processor are provided. In one embodiment, a plurality of instructions stored in the...
7228528 Building inter-block streams from a dynamic execution trace for a program  
In one embodiment, the invention provides a method for the processing of instructions. A method which comprises analyzing a dynamic execution trace for a program; identifying at least one stream...
7155574 Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory  
A high-speed memory management technique that minimizes clobber in sequentially accessed memory, including but not limited to, for example, a trace cache. The method includes selecting a victim...
7134124 Thread ending method and device and parallel processor system  
Each processor comprises a register for storing start address of a forked child thread and a comparator for detecting that the value of its own program counter is coincident with the start address...
7096343 Method and apparatus for splitting packets in multithreaded VLIW processor  
A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional...
7020769 Method and system for processing a loop of instructions  
An information handling system processes a loop of instructions. In response to detecting processing of a particular instruction during a pass through the loop, the system initiates a fetch of an...
6804770 Method and apparatus for using past history to avoid flush conditions in a microprocessor  
A hazard prediction array consists of an array of saturating counters. The array is indexed through a portion of the instruction address. At issue, the hazard prediction array is referenced and a...
6789186 Method and apparatus to reduce penalty of microcode lookup  
A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The...
6677955 Image processing method and image processing apparatus  
The present invention is characterized by first performing the necessary rendering in the frame period, then during the remaining time of that frame period, rewriting the texture data in the...
6671799 System and method for dynamically sizing hardware loops and executing nested loops in a digital signal processor  
There is disclosed, for use in a digital signal processor, an apparatus for dynamically sizing a hardware loop that executes a plurality of instruction sequences forming a plurality of instruction...
6665791 Method and apparatus for releasing functional units in a multithreaded VLIW processor  
A method and apparatus are disclosed for releasing functional units in a multithreaded very large instruction word (VLIW) processor. The functional unit release mechanism can retrieve the capacity...
6625726 Method and apparatus for fault handling in computer systems  
A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first...
6457119 Processor instruction pipeline with error detection scheme  
Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source...
6349405 Packet classification state machine  
A method of reprogramming classification data in a packet classification state machine without interrupting the operation of the state machine is disclosed. Data relating to a plurality of new...
6301651 Method and apparatus for folding a plurality of instructions  
The present invention provides a stack machine for executing a plurality of instructions one by one. The stack machine comprises an operation folder and an execution unit. The operation folder is...
6289444 Method and apparatus for subroutine call-return prediction  
A method for associating subroutine calls with corresponding targets includes the step of maintaining a first table of entries. Each entry in the first table includes: a first table first address...
6192468 Apparatus and method for detecting microbranches early  
A superscalar microprocessor implements a microcode instruction unit with sequence control fields appended to each microcode line. The sequence control fields indicate whether a subsequent line...
6185673 Apparatus and method for array bounds checking with a shadow register file  
A circuit for processing source code with associated array bounds limitations includes an execution unit that generates a register value signal and an index number signal corresponding to an array...
6175913 Data processing unit with debug capabilities using a memory protection unit  
A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A...
6151670 Method for conserving memory storage using a pool of short term memory registers  
A method for conserving processor registers during the execution of a program in which short term data having a short processing period and long term data having a long processing period are...
6134645 Instruction completion logic distributed among execution units for improving completion efficiency  
Each execution unit within a superscalar processor has an associated completion table that contains a copy of the status of all instructions dispatched but not completed. A central completion...
6122728 Technique for ordering internal processor register accesses  
A technique for processing register instructions in a pipeline data processor in which multiple instructions may be processed concurrently, and may therefore conflict with one another. Register...
6119219 System serialization with early release of individual processor  
A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode...
6101598 Methods for debugging a multiprocessor system  
A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is...
6079013 Multiprocessor serialization with early release of processors  
A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode...
6014741 Apparatus and method for predicting an end of a microcode loop  
A superscalar microprocessor implements a microcode instruction unit that predicts the end of microcode loops. The microcode instruction unit detects a microcode loop and begins counting the...
6009454 Multi-tasking operation system for industrial controller  
A multi-tasking operating system for real-time control of industrial processes integrates ladder type programs and state-type programs by viewing each as a series of instructions with an implicit...
5987594 Apparatus for executing coded dependent instructions having variable latencies  
A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a...
5928337 Programmable image processing system including scanner with displaying device for sequential display of control signals when script file execution program starts  
An image processing system having programmable keys for recording frequently used procedures is disclosed. The scanner comprises a scanning module for scanning an document, a plurality of...
5794026 Microprocessor having expedited execution of condition dependent instructions  
A processor architecture and methodology for executing a condition dependent instruction over a plurality of execution stages in a microprocessor. The microprocessor includes a memory for storing...
5761476 Non-clocked early read for back-to-back scheduling of instructions  
A mechanism and method providing an early read operation of data associated with an instruction dispatched for execution to provide data dependency information in time to be used for scheduling...
5761509 System and method for enabling before/after method processing in an object oriented system  
A system for creating before and after behavior upon invocation of a method in an object-oriented system. The framework provides metaclasses containing methods for dispatching a before method and...
5752030 Program execution control in parallel processor system for parallel execution of plural jobs by selected number of processors  
In submitting each job in a parallel processing system provided with a plurality of processors, execution conditions such as a requested minimum processor number, an upper limit used processor...
5717902 Method and system for selectively applying an appropriate object ownership model  
A method and system for applying an appropriate object ownership model is provided. In a preferred embodiment, an operating system selectively applies an object ownership model with which running...
5694613 Hardware arrangement of effectively expanding data processing time in pipelining in a microcomputer system and a method thereof  
A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangment is provided with a plurality of stages each of which has a temporary...
5452425 Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words  
A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words...
5432933 Method of canceling a DB2 thread  
A DB2 thread cancellation method permits operator intervention to terminate a DB2 thread. After the thread to be canceled has been located, a series of one or more SRBs is scheduled to cancel the...
5299318 Processor with a plurality of microprogrammed units, with anticipated execution indicators and means for executing instructions in pipeline manner  
A data processing system having processors with large instruction sets optimized for the execution of brief instructions. The processor (CPU) comprises a plurality of microprogrammed execution...

Matches 1 - 50 out of 61 1 2 >