|
Match
|
Document |
Document Title |
|
|
8179540 |
Image forming apparatus and management system utilizing counter and job log information for usage tracking
An image forming apparatus is provided that holds counter information obtained by integrating a consumption of a consumable that depends on usage of service provided by the image forming apparatus....
|
|
|
8140831 |
Routing instructions in a processor
Disclosed are a method and system for reducing complexity of routing of instructions from an instruction issue queue to appropriate execution pipelines in a superscalar processor. In one or more...
|
|
|
8074060 |
Out-of-order execution microprocessor that selectively initiates instruction retirement early
A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an...
|
|
|
8074052 |
System and method for assigning tags to control instruction processing in a superscalar processor
A tag monitoring system for assigning tags to instructions embodied in software on a tangible computer-readable storage medium. A source supplies instructions to be executed by a functional unit. A...
|
|
|
8068109 |
Processor task and data management
Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two or...
|
|
|
8019975 |
System and method for handling load and/or store operations in a superscalar microprocessor
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
|
|
|
7966478 |
Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers
A method for reducing entries searched in a load reorder queue (LRQ) when snoop instructions are executed by a processor, including checking load reorder queue (LRQ) entries located between a...
|
|
|
7941635 |
High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution
The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements...
|
|
|
7941636 |
RISC microprocessor architecture implementing multiple typed register sets
Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is...
|
|
|
7926062 |
Interrupt and exception handling for multi-streaming digital processors
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...
|
|
|
7900207 |
Interrupt and exception handling for multi-streaming digital processors
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...
|
|
|
7844797 |
System and method for handling load and/or store operations in a superscalar microprocessor
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
|
|
|
7840788 |
Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register
A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a pipelined...
|
|
|
7822881 |
Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially...
|
|
|
7802074 |
Superscalar RISC instruction scheduling
A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a...
|
|
|
7739482 |
High-performance, superscalar-based computer system with out-of-order instruction execution
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality...
|
|
|
7734897 |
Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads
A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process...
|
|
|
7734827 |
Operation of cell processors
Secure operation of cell processors is disclosed. A cell processor receives a secure file image from a client device at a cell processor of a host device (host cell processor), wherein the secure...
|
|
|
7712080 |
Systems and methods for parallel distributed programming
The present invention relates generally to computer programming, and more particularly to systems and methods for parallel distributed programming. Generally, a parallel distributed program is...
|
|
|
7711934 |
Processor core and method for managing branch misprediction in an out-of-order processor pipeline
A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch...
|
|
|
RE41293 |
Multiprocessor computer having configurable hardware system domains
Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system...
|
|
|
7694112 |
Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation
A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to...
|
|
|
7685402 |
RISC microprocessor architecture implementing multiple typed register sets
A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such...
|
|
|
7664935 |
System and method for translating non-native instructions to native instructions for processing on a host processor
A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning...
|
|
|
7653804 |
Resource sharing in multiple parallel pipelines
A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated...
|
|
|
7590824 |
Mixed superscalar and VLIW instruction issuing and processing method and system
Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal...
|
|
|
7562206 |
Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions
Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are...
|
|
|
7533248 |
Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor
A multithreaded processor including a shared functional unit. In one embodiment, the multithreaded processor includes a functional unit coupled to a multithreaded instruction source that may...
|
|
|
7506185 |
Selective power-down for high performance CPU/system
A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy...
|
|
|
7490225 |
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number
Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in...
|
|
|
7467286 |
Executing partial-width packed data instructions
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the...
|
|
|
7467385 |
Interrupt and exception handling for multi-streaming digital processors
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...
|
|
|
7464242 |
Method of load/store dependencies detection with dynamically changing address length
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming...
|
|
|
7460989 |
Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language
A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs...
|
|
|
7447876 |
System and method for handling load and/or store operations in a superscalar microprocessor
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
|
|
|
7430651 |
System and method for assigning tags to control instruction processing in a superscalar processor
A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each...
|
|
|
7409670 |
Scheduling logic on a programmable device implemented using a high-level language
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written...
|
|
|
7401328 |
Software-implemented grouping techniques for use in a superscalar data processing system
A data processing system includes a grouping tool coupled to a processor. The grouping tool groups the stream of instructions such that each group of instructions has a dimensionless signature...
|
|
|
7398375 |
Technique for reduced-tag dynamic scheduling and reduced-tag prediction
The present invention provides a dynamic scheduling scheme that uses reservation stations having at least one station that stores an at least two operand instruction. An allocator portion...
|
|
|
7392369 |
Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check
Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine...
|
|
|
7376812 |
Vector co-processor for configurable and extensible processor architecture
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one...
|
|
|
7373481 |
Distributed-structure-based parallel module structure and parallel processing method
A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1...
|
|
|
7373485 |
Clustered superscalar processor with communication control between clusters
A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction...
|
|
|
7330963 |
Resolving all previous potentially excepting architectural operations before issuing store architectural operation
Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine...
|
|
|
7318145 |
Random slip generator
A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be...
|
|
|
7308559 |
Digital signal processor with cascaded SIMD organization
A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD...
|
|
|
7281119 |
Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes
A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and...
|
|
|
7254693 |
Selectively prohibiting speculative execution of conditional branch type based on instruction bit
A method, apparatus, and computer program product are disclosed for selectively prohibiting speculative conditional branch execution. A particular type of conditional branch instruction is...
|
|
|
7249243 |
Control word prediction and varying recovery upon comparing actual to set of stored words
Techniques for control word prediction and speculative execution. In one embodiment, an apparatus includes a control word predictor, execution resources, and a comparison module. The control word...
|
|
|
7225320 |
Control architecture for a high-throughput multi-processor channel decoding system
A multi-processor unit includes a first domain for processing data according to first configuration information and having multiple first domain processors each connected to communication apparatus...
|