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9009506 Energy efficient microprocessor platform based on instructional level parallelism  
Embodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates...
8924661 Memory system including a controller and processors associated with memory devices  
A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept...
8812822 Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss  
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for minimizing unscheduled D-cache miss pipeline stalls is provided. The...
8775147 Algorithm and architecture for multi-argument associative operations that minimizes the number of components using a latency of the components  
An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for...
8649508 System and method for implementing elliptic curve scalar multiplication in cryptography  
A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further...
8645714 Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions  
A branch target address cache (BTAC) caches history information associated with branch and switch key instructions previously executed by a microprocessor. The history information includes a...
8566570 Distributed multi-core memory initialization  
In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute...
8516223 Dispatching instruction from reservation station to vacant instruction queue of alternate arithmetic unit  
A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag...
8468540 Interrupt and exception handling for multi-streaming digital processors  
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...
8464089 Tracing apparatus and tracing system  
A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of...
8402256 Processing prefix code in instruction queue storing fetched sets of plural instructions in superscalar processor  
The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an...
8307198 Distributed multi-core memory initialization  
In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute...
8261085 Methods, apparatus and systems to improve security in computer systems  
According to some implementations methods, apparatus and systems are provided involving the use of processors having at least one core with a security component, the security component adapted to...
8250395 Dynamic voltage and frequency scaling (DVFS) control for simultaneous multi-threading (SMT) processors  
A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the...
8245015 Processor monitoring execution of a synchronization instruction issued to execution sections to detect completion of execution of preceding instructions in an identified thread  
A processor includes a plurality of executing sections configured to simultaneously execute instructions for a plurality of threads, an instruction issuing section configured to issue instructions...
8219784 Assigning and pre-decoding group ID and tag ID prior to dispatching instructions in out-of-order processor  
A computer-implemented method and apparatus for managing an out of order dispatched instruction queue in a microprocessor. In one embodiment, the method and apparatus include assigning a group...
8200950 Sharing pipeline by inserting NOP to accommodate memory access request received from other processors  
A pipeline operation processor comprises a pipeline processing unit and an instruction insertion controller which inserts an instruction when access to an operation memory is requested, and...
8195759 Performing externally assisted calls in a heterogeneous processing complex  
A mechanism is provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second processor by performing an assisted...
8179540 Image forming apparatus and management system utilizing counter and job log information for usage tracking  
An image forming apparatus is provided that holds counter information obtained by integrating a consumption of a consumable that depends on usage of service provided by the image forming...
8140831 Routing instructions in a processor  
Disclosed are a method and system for reducing complexity of routing of instructions from an instruction issue queue to appropriate execution pipelines in a superscalar processor. In one or more...
8074052 System and method for assigning tags to control instruction processing in a superscalar processor  
A tag monitoring system for assigning tags to instructions embodied in software on a tangible computer-readable storage medium. A source supplies instructions to be executed by a functional unit....
8074060 Out-of-order execution microprocessor that selectively initiates instruction retirement early  
A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an...
8068109 Processor task and data management  
Task and data management systems methods and apparatus are disclosed. A processor event that requires more memory space than is available in a local storage of a co-processor is divided into two...
8019975 System and method for handling load and/or store operations in a superscalar microprocessor  
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
7966478 Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers  
A method for reducing entries searched in a load reorder queue (LRQ) when snoop instructions are executed by a processor, including checking load reorder queue (LRQ) entries located between a...
7941635 High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution  
The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements...
7941636 RISC microprocessor architecture implementing multiple typed register sets  
Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is...
7926062 Interrupt and exception handling for multi-streaming digital processors  
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...
7900207 Interrupt and exception handling for multi-streaming digital processors  
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...
7844797 System and method for handling load and/or store operations in a superscalar microprocessor  
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
7840788 Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register  
A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a...
7822881 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)  
In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes...
7802074 Superscalar RISC instruction scheduling  
A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a...
7739482 High-performance, superscalar-based computer system with out-of-order instruction execution  
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality...
7734827 Operation of cell processors  
Secure operation of cell processors is disclosed. A cell processor receives a secure file image from a client device at a cell processor of a host device (host cell processor), wherein the secure...
7734897 Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads  
A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process...
7712080 Systems and methods for parallel distributed programming  
The present invention relates generally to computer programming, and more particularly to systems and methods for parallel distributed programming. Generally, a parallel distributed program is...
7711934 Processor core and method for managing branch misprediction in an out-of-order processor pipeline  
A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch...
RE41293 Multiprocessor computer having configurable hardware system domains  
Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system...
7694112 Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation  
A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to...
7685402 RISC microprocessor architecture implementing multiple typed register sets  
A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such...
7664935 System and method for translating non-native instructions to native instructions for processing on a host processor  
A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning...
7653804 Resource sharing in multiple parallel pipelines  
A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated...
7590824 Mixed superscalar and VLIW instruction issuing and processing method and system  
Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal...
7562206 Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions  
Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are...
7533248 Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor  
A multithreaded processor including a shared functional unit. In one embodiment, the multithreaded processor includes a functional unit coupled to a multithreaded instruction source that may...
7506185 Selective power-down for high performance CPU/system  
A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy...
7490225 Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number  
Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution...
7467286 Executing partial-width packed data instructions  
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the...
7467385 Interrupt and exception handling for multi-streaming digital processors  
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...