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7590824 |
Mixed superscalar and VLIW instruction issuing and processing method and system
Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal...
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7562206 |
Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions
Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are...
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7555631 |
RISC microprocessor architecture implementing multiple typed register sets
A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such...
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7533248 |
Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor
A multithreaded processor including a shared functional unit. In one embodiment, the multithreaded processor includes a functional unit coupled to a multithreaded instruction source that may...
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7506185 |
Selective power-down for high performance CPU/system
A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy...
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7490225 |
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number
Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in...
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7467385 |
Interrupt and exception handling for multi-streaming digital processors
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...
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7467286 |
Executing partial-width packed data instructions
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the...
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7464242 |
Method of load/store dependencies detection with dynamically changing address length
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming...
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7460989 |
Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language
A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs...
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7447876 |
System and method for handling load and/or store operations in a superscalar microprocessor
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
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7430651 |
System and method for assigning tags to control instruction processing in a superscalar processor
A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each...
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7409670 |
Scheduling logic on a programmable device implemented using a high-level language
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written...
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7401328 |
Software-implemented grouping techniques for use in a superscalar data processing system
A data processing system includes a grouping tool coupled to a processor. The grouping tool groups the stream of instructions such that each group of instructions has a dimensionless signature...
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7398375 |
Technique for reduced-tag dynamic scheduling and reduced-tag prediction
The present invention provides a dynamic scheduling scheme that uses reservation stations having at least one station that stores an at least two operand instruction. An allocator portion...
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7392369 |
Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check
Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine...
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7376812 |
Vector co-processor for configurable and extensible processor architecture
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one...
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7373485 |
Clustered superscalar processor with communication control between clusters
A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction...
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7373481 |
Distributed-structure-based parallel module structure and parallel processing method
A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1...
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7343473 |
System and method for translating non-native instructions to native instructions for processing on a host processor
A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning...
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7330963 |
Resolving all previous potentially excepting architectural operations before issuing store architectural operation
Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine...
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7318145 |
Random slip generator
A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be...
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7308559 |
Digital signal processor with cascaded SIMD organization
A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD...
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7281119 |
Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes
A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and...
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7254693 |
Selectively prohibiting speculative execution of conditional branch type based on instruction bit
A method, apparatus, and computer program product are disclosed for selectively prohibiting speculative conditional branch execution. A particular type of conditional branch instruction is...
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7249243 |
Control word prediction and varying recovery upon comparing actual to set of stored words
Techniques for control word prediction and speculative execution. In one embodiment, an apparatus includes a control word predictor, execution resources, and a comparison module. The control word...
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7225320 |
Control architecture for a high-throughput multi-processor channel decoding system
A multi-processor unit includes a first domain for processing data according to first configuration information and having multiple first domain processors each connected to communication apparatus...
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7210024 |
Conditional instruction execution via emissary instruction for condition evaluation
Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the...
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7200737 |
Processor with a replay system that includes a replay queue for improved throughput
A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to...
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7171541 |
Register renaming system
A register renaming system for a processor based on superscalar architecture that can process a larger number of instructions per cycle by providing a free list to hold unallocated...
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7143401 |
Single-chip multiprocessor with cycle-precise program scheduling of parallel execution
A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor...
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7136989 |
Parallel computation processor, parallel computation control method and program thereof
A parallel computation processor being capable of high-speed loop operation. When instruction decoders decode the VLOOP instruction, which triggers loop operation, an instruction buffer starts...
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7111152 |
Computer system that operates in VLIW and superscalar modes and has selectable dependency control
Instructions in a computer system are executed in a plurality of parallel execution pipelines, a horizontal dependency check is carried out between instructions supplied to the parallel pipelines...
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7096347 |
Processor and method of testing a processor for hardware faults utilizing a pipeline interlocking test instruction
The instruction pipeline of a processor, which includes execution circuitry and instruction sequencing logic, receives a stream of instructions including a pipeline interlocking test instruction....
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7089404 |
Method and apparatus for enhancing scheduling in an advanced microprocessor
Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply...
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7062636 |
Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation
Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine...
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7058795 |
Method and apparatus of branch prediction
Briefly, a method and apparatus of branch prediction is provided. The branch prediction may be done by performing a XOR operation between MSB of set bits of a path register with LSB of set bits of...
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7051187 |
Superscalar RISC instruction scheduling
A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a...
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7028161 |
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements...
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7024542 |
System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions
A processor system and method that reduces the number of register value copying made from alias registers to corresponding real (architectural) registers. One method entails not performing an alias...
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7020879 |
Interrupt and exception handling for multi-streaming digital processors
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler...
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7000135 |
Clock control method and information processing device employing the clock control method
In an information processing device including a processing circuit that performs processing in synchronization with a clock, and a clock supply control circuit that controls supply of the clock to...
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6996698 |
Blocking processing restrictions based on addresses
Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an...
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6978460 |
Processor having priority changing function according to threads
A time multiplex changing function for priorities among threads is added to a multi-thread processor, and capability for large-scale out-of-order execution is achieved by confining the flows of...
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6965987 |
System and method for handling load and/or store operations in a superscalar microprocessor
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
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6928533 |
Data processing system and method for implementing an efficient out-of-order issue mechanism
An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for...
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6925550 |
Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection
A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at...
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6895497 |
Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority
A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource...
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6880067 |
Retiring instructions that meet the early-retirement criteria to improve computer operation throughput
Techniques are provided for retiring instructions that typically complete early as compared to most instructions. In an embodiment, all instructions are processed normally until the instruction...
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6862676 |
Superscalar processor having content addressable memory structures for determining dependencies
A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an...
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