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5923872 |
Apparatus for sampling instruction operand or result values in a processor pipeline
An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a...
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5920710 |
Apparatus and method for modifying status bits in a reorder buffer with a large speculative state
A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. To reduce the time delay for identifying mispredicted instructions, prioritizing...
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5911057 |
Superscalar microprocessor having combined register and memory renaming circuits, systems, and methods
Circuits, systems, and methods of operating a processor (110) to process a plurality of instructions, wherein each of the plurality of instructions has a respective sequence number. Further,...
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5909588 |
Processor architecture with divisional signal in instruction decode for parallel storing of variable bit-width results in separate memory locations
An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division...
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5907714 |
Method for pipelined data processing with conditioning instructions for controlling execution of instructions without pipeline flushing
A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to...
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5904732 |
Dynamic priority switching of load and store buffers in superscalar processor
A method and apparatus for dynamically switching the relative priorities of the load buffer and store buffer with respect to external memory resources in a superscalar processor. According to a...
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5906002 |
Method and apparatus for saving and restoring the context of registers using different instruction sets for different sized registers
A method of saving the context of a plurality of registers in a computer processor, requires determining whether the processor registers have a first size or a second size, and saving the contents...
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5898882 |
Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage
A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for...
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5894582 |
Method of controlling parallel processing at an instruction level and processor for realizing the method
Apparatus for realizing instruction level parallel processing includes an instruction buffer for storing instructions fetched from a memory until the instructions are sent from the instruction...
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5894549 |
System and method for fault detection in microcontroller program memory
A method for fault detection in microcontroller program memory includes a new move instruction. An address of program instruction data is placed in a word register and a mode register. The new...
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5892936 |
Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register
A superscalar microprocessor configured to speculatively generate register values associated with a particular register is provided. Multiple register values are generated in parallel, wherein each...
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5892963 |
System and method for assigning tags to instructions to control instruction execution
Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions....
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5889974 |
Method and apparatus for the detection of reordering hazards
In a computer system processing out of order commands, a method for detecting situations in which errors could be caused by execution of an out of order command. The method includes the steps of...
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5887185 |
Interface for coupling a floating point unit to a reorder buffer
A microprocessor has an interface between a reorder buffer and a floating point unit, including a retire signal provided by the reorder buffer and a valid signal provided by the floating point...
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5887161 |
Issuing instructions in a processor supporting out-of-order execution
The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a...
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5884057 |
Temporal re-alignment of a floating point pipeline to an integer pipeline for emulation of a load-operate architecture on a load/store processor
A processor that can execute both CISC and RISC instructions has an integer pipeline and a floating point pipeline. RISC instructions are sent to the floating point pipeline at the beginning of the...
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5881306 |
Instruction fetch bandwidth analysis
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an...
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5881261 |
Processing system that rapidly indentifies first or second operations of selected types for execution
A processing system includes sequential entries for storing operations of different types and a scan chain which can identify an operation of a first type which follows after an operation of a...
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5881307 |
Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor
A superscalar processor includes an execution unit that executes load/store instructions and an execution unit that executes arithmetic instruction. Execution pipelines for both execution units...
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5881308 |
Computer organization for multiple and out-of-order execution of condition code testing and setting instructions out-of-order
Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction...
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5881256 |
Bus interface unit capable of simultaneously proceeding with two bus cycles in a high-performance microprocessor
A bus interface unit of a microprocessor which can simultaneously process bus cycle's requests coming from various pipelines during for one cycle in the pipelined high-performance microprocessor of...
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5872989 |
Processor having a register configuration suited for parallel execution control of loop processing
A method and apparatus for handling a large-capacity register file by using a small instruction field as to support a software pipeline. The invention includes a register file having a plurality of...
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5872949 |
Apparatus and method for managing data flow dependencies arising from out-of-order execution, by an execution unit, of an instruction series input from an instruction source
An apparatus and method to manage data flow dependencies so that a processor can complete instructions and write associated data to architected logical registers out of the program order. This...
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5872965 |
System and method for performing multiway branches using a visual instruction set
An innovative method and system of performing multiway branch operations on a microprocessor architecture which supports single instruction multiple data (SIMD) operations is provided. A computer...
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5870582 |
Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched
In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution...
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5870575 |
Indirect unconditional branches in data processing system emulation mode
A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, a series of...
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5870578 |
Workload balancing in a microprocessor for reduced instruction dispatch stalling
A microprocessor employs a set of symmetrical functional units, each of which is coupled into an issue position. Instructions are fetched and aligned to the issue positions. During clock cycles in...
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5870618 |
Processor and data processor
An object of the present invention is to provide a processor which can execute calculation between data of a data length larger than the data length of the register file at high speed without the...
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5870580 |
Decoupled forwarding reorder buffer configured to allocate storage in chunks for instructions having unresolved dependencies
A reorder buffer is provided which decouples allocation of storage space within the buffer for storing instructions from forwarding of the corresponding operands. When instructions are presented to...
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5870579 |
Reorder buffer including a circuit for selecting a designated mask corresponding to an instruction that results in an exception
A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. The reorder buffer stores speculatively executed instructions until the instructions...
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5867683 |
Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations
A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and...
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5867725 |
Concurrent multitasking in a uniprocessor
A superscalar uniprocessor that performs concurrent multi-task processing is provided. The processor of the present invention maintains a complete set of program address, memory control and general...
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5867684 |
Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction
A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store...
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5867680 |
Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions
An instruction dispatch apparatus is provided in which a directly-decoded instruction and a microcode instruction are concurrently dispatched ("packed"). The instruction which is second in program...
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5860018 |
Method for tracking pipeline resources in a superscalar processor
A method and apparatus for tracking pipeline resources of a processor involves fetching selected ones of the coded instructions and marking the fetched instructions with instruction metadata. The...
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5859998 |
Hierarchical microcode implementation of floating point instructions for a microprocessor
A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses...
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5857096 |
Microarchitecture for implementing an instruction to clear the tags of a stack reference register file
An apparatus (e.g. a microarchitecture of a microprocessor) comprising a plurality of tags associated with a first storage area indicating that locations in the first storage area are either empty...
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5852726 |
Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner
A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is...
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5850533 |
Method for enforcing true dependencies in an out-of-order processor
In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an...
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5850563 |
Processor and method for out-of-order completion of floating-point operations during load/store multiple operations
A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's...
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5848287 |
Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches
A superscalar microprocessor is provided which maintains coherency between a pair of caches accessed from different stages of an instruction processing pipeline. A dependency checking structure is...
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5842036 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for...
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5842031 |
Advanced parallel array processor (APAP)
A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a...
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5838941 |
Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers
An advanced register renamer comprises an associative memory having a plurality of entries, each entry storing a representation of a single operation as an expression paired with a corresponding...
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5835745 |
Hardware instruction scheduler for short execution unit latencies
A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions,...
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5835748 |
Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file
A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to...
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5832293 |
Processor architecture providing speculative, out of order execution of instructions and trap handling
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic...
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5832297 |
Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations
A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Because each storage location may contain either a load or a store...
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5828873 |
Assembly queue for a floating point unit
A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses...
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5828895 |
Methods and system for predecoding instructions in a superscalar data processing system
In response to reloading an instruction from main memory for storing in an instruction cache in a superscalar data processing system, a particular instruction category in which the instruction...
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