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6714961 |
Multiple job signals per processing unit in a multiprocessing system
The invention is directed toward a multiprocessing system having multiple processing units. For at least one of the processing units in the multiprocessing system, a first job signal is assigned to...
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6711670 |
System and method for detecting data hazards within an instruction group of a compiled computer program
A superscalar processing system that detects data hazards within instruction groups utilizes a memory, a plurality of pipelines, an instruction dispersal unit (IDU), and a control mechanism. The...
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6708269 |
Method and apparatus for multi-mode fencing in a microprocessor system
In a multi-threaded system, such as in a multi-processor system, different types of fences are provided to force completion of programmatically earlier instructions in a program. The types of...
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6704856 |
Method for compacting an instruction queue
A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits...
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6694424 |
Store load forward predictor training
A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous...
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6691240 |
System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient way
A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the...
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6691221 |
Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution
A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the...
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6675288 |
Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list
A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of...
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6658550 |
Pipelined asynchronous processing
An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to...
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6651161 |
Store load forward predictor untraining
A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous...
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6651164 |
System and method for detecting an erroneous data hazard between instructions of an instruction group and resulting from a compiler grouping error
A superscalar processing system that detects data hazards within instruction groups transmitted to the processing system utilizes a content-addressable memory, a plurality of pipelines, an...
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6651159 |
Floating point register stack management for CISC
A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose...
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6647486 |
Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and processing of routine data
Routine processing for routine data, non-routine processing for routine data and general non-routine processing are to be processed efficiently. To this end, a main CPU has a CPU core having a...
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6643766 |
Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor
Speculative pre-fetching and pre-flushing of additional cache lines minimize cache miss latency and coherency check latency of an out of order instruction execution processor. A pre-fetch/pre-flush...
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6633970 |
Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer
A mechanism is provided for allowing a processor to recover from a failure of a predicted path of instructions (e.g., from a mispredicted branch or other event). The mechanism includes a plurality...
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6631462 |
Memory shared between processing threads
A method includes pushing a datum onto a stack by a first processor and popping the datum off the stack by a second processor.
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6631464 |
Instruction pipeline with a branch prefetch when the branch is certain
An instruction fetch control system prefetches a branch instruction in a pipeline system and fetches a branch target instruction of the branch instruction. The control system comprises a first...
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6629232 |
Copied register files for data processors having many execution units
Interconnect-dominated large register files are reduced in chip area and delay time. A register file in a processor having a number of execution units is divided into multiple copies. Different...
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6625726 |
Method and apparatus for fault handling in computer systems
A method and apparatus for fault handling in computer systems. In one embodiment, a first register is used to store an address which points to the top of a stack. The address stored in the first...
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6622235 |
Scheduler which retries load/store hit situations
A scheduler issues memory operations without regard to whether or not resources are available to handle each possible execution outcome of that memory operation. The scheduler also retains the...
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6609189 |
Cycle segmented prefix circuits
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing...
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6609247 |
Method and apparatus for re-creating the trace of an emulated instruction set when executed on hardware native to a different instruction set field
A method and an apparatus for re-creating a trace of instructions from an emulated instruction set when running on hardware optimized for a different instruction set, such as IA-32 instructions...
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6591360 |
Local stall/hazard detect in superscalar, pipelined microprocessor
A method and apparatus that generates a simplified, localized version (“a local stall”) of a global stall to improve the performance of a pipelined microprocessor. The local stall is generated whe...
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6574725 |
Method and mechanism for speculatively executing threads of instructions
A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute...
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6567839 |
Thread switch control in a multithreaded processor system
A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of...
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6560692 |
Data processing circuit, microcomputer, and electronic equipment
The data processing circuit of this invention enables efficient description and execution of processes that act upon the stack pointer, using short instructions. It also enables efficient...
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6553480 |
System and method for managing the execution of instruction groups having multiple executable instructions
A group completion table (GCT) that manages the execution of instruction groups having more than one executable instruction is disclosed. The GCT includes a plurality of table entries, wherein each...
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6542986 |
Resolving dependencies among concurrently dispatched instructions in a superscalar microprocessor
A superscalar processor may issue multiple instructions per clock cycle. Included in a superscalar processor may be a reorder buffer which stores information corresponding to concurrently...
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6526499 |
Method and apparatus for load buffers
The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then...
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6522934 |
Dynamic unit selection in a process control system
A process control system includes a controller that executes a control routine which performs a series of unit procedures within a process. The control routine is written or created to specify the...
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6515759 |
Printer having processor with instruction cache and compressed program store
A printer provides additional read/write memory for image processing by operating with stored programs in compressed form. When needed for execution, instructions of a compressed program are...
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6499099 |
Central processing unit method and apparatus for extending general instructions with extension data of an extension register
A central processing unit having an extension instruction comprises a memory address, an offset and a fixed length instruction of varying immediate data. The central processing unit comprises a...
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6487652 |
Method and apparatus for speculatively locking objects in an object-based system
Methods and apparatus for speculatively locking an object are disclosed. According to one aspect of the present invention, a method for acquiring use of an object using a current thread includes a...
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6484254 |
Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses
According to one aspect of the invention, a method is provided in which store addresses of store instructions dispatched during a last predetermined number of cycles are maintained in a first data...
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6484251 |
Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor
A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky...
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6477562 |
Prioritized instruction scheduling for multi-streaming processors
A multi-streaming processor has multiple streams for processing multiple threads, and an instruction scheduler including a priority record of priority codes for one or more of the streams. The...
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6463525 |
Merging single precision floating point operands
Where it is desired to perform a double precision operation using single precision operands, first and second single precision operands are loaded into first and second respective rows of a...
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6453344 |
Multiprocessor servers with controlled numbered of CPUs
A multiprocessor system having a total number of available CPUs partitioned into one or more smaller pools of CPUs called servers where the number of CPUs available to a server is reduced below the...
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6442670 |
Data processing system including a shared memory resource circuit
A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing...
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6438680 |
Microprocessor
When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following...
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6438677 |
Dynamic handling of object versions to support space and time dimensional program execution
One embodiment of the present invention provides a system that supports space and time dimensional program execution by facilitating accesses to different versions of a memory element. The system...
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6434689 |
Data processing unit with interface for sharing registers by a processor and a coprocessor
An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution...
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6415354 |
Pipelined methods and apparatus for weight selection and content addressable memory searches
When a search key is supplied to a content addressable memory (CAM), the CAM signals indicate which CAM entries have matched the key. These signals are provided to a weight array to select the...
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6412062 |
Injection control mechanism for external events
The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified....
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6412061 |
Dynamic pipelines with reusable logic elements controlled by a set of multiplexers for pipeline stage selection
A method of dynamically adjusting a multiple stage pipeline to execute one of a set of instructions, wherein each stage has a latency and performs a selected data operation. An instruction to be...
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6408377 |
Dynamic allocation of resources in multiple microprocessor pipelines
A microprocessor having M parallel pipelines and N arithmetic logic units, where N is less than M. A single instruction fetch stage fetches multi-stage instructions, and a single instruction...
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6405304 |
Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list
A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of...
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6397319 |
Process for executing highly efficient VLIW
A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation...
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6385719 |
Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor
A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher....
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6385715 |
Multi-threading for a processor utilizing a replay queue
A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to...
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