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7634641 Method and apparatus for using multiple threads to spectulatively execute instructions  
One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system staffs by executing instructions in normal execution mode using a first...
7634637 Execution of parallel groups of threads with per-instruction serialization  
In a processor, a SIMD group (a group of threads for which instructions are issued in parallel using single instruction, multiple data instruction issue techniques) is logically divided into two or...
7634609 Data transmission coordinating method  
In a data transmission coordinating method, the computer system enters a coordinating state, and a first signal is issued from the central processing unit to the data transmission standard storage...
RE41012 Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor  
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the...
7603543 Method, apparatus and program product for enhancing performance of an in-order processor with long stalls  
A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data...
7603566 Authenticated process switching on a microprocessor  
A microprocessor includes a first information holding unit, a second information holding unit, and a switching authorization unit. The first information holding unit holds process identification...
7596682 Architected register file system utilizes status and control registers to control read/write operations between threads  
An apparatus, a method, and a computer program are provided for an architected register file system for multithread system. In conventional architected register file systems, a thread is only...
7594102 Method and apparatus for vector execution on a scalar machine  
A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times...
7581037 Effecting a processor operating mode change to execute device code  
Provided are a method, system and program for effecting a processor operating mode change to execute device code. A processor receives a call while the processor is operating in a first mode,...
7568055 Data processing apparatus for selecting either a PIO data transfer method or a DMA data transfer method  
The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit...
7568083 Memory mapped register file and method for accessing the same  
A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by...
7559061 Simultaneous multi-threading control monitor  
One example would provide for maximum throughput thus increasing capacity during times when only low and medium priority work is running while allowing for the shorter turn around times required by...
7539852 Processor resource management  
Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution...
7529912 Apparatus and method for instruction-level specification of floating point format  
Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an...
7529916 Data processing apparatus and method for controlling access to registers  
A data processing apparatus and method are provided for controlling access to registers. The data processing apparatus comprises a processing unit for performing data processing operations on data...
7509484 Handling cache misses by selectively flushing the pipeline  
An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT processor keeps track of load misses...
7509480 Selection of ISA decoding mode for plural instruction sets based upon instruction address  
An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to...
7500126 Arrangement and method for controlling power modes of hardware resources  
A circuit arrangement, method of executing program code and method of generating program code utilize power control instructions ( 90 ) capable of dynamically controlling power dissipation of...
7493472 Meta-address architecture for parallel, dynamically reconfigurable computing  
A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a...
7493621 Context switch data prefetching in multithreaded computer  
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
7490178 Threshold on unblocking a processing node that is blocked due data packet passing  
A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the...
7480754 Assignment of queue execution modes using tag values  
The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host....
7475393 Method and apparatus for parallel computations with incomplete input operands  
A method and apparatus for performing pipelined computations that include cross-iteration computations. The apparatus includes a functional unit having at least one input and an output, each input...
7451298 Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode  
One embodiment of the present invention provides a system that uses an M-bit operating system (OS) kernel to support N-bit user processes. During operation, the system receives an exception. Note...
7447874 Method and system for designing a flexible hardware state machine  
Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the...
7447880 Processor with internal memory configuration  
A processor comprises an arithmetic unit for processing operands, a register memory for storing operands with a register memory space and a register memory configuration unit. The register memory...
7444488 Method and programmable unit for bit field shifting  
A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first...
7444500 Method for executing a 32-bit flat address program during a system management mode interrupt  
A method and system for executing 32-bit flat address programs during a System Management Interrupt. The system provides a 16-bit SMI routine that is given control when an SMI occurs. That routine...
7437542 Identifying and processing essential and non-essential code separately  
A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate...
7437532 Memory mapped register file  
A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by...
7437724 Registers for data transfers  
A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a...
7434029 Inter-processor control  
A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an...
7430678 Low power operation control unit and program optimizing method  
An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit...
7421571 Apparatus and method for switching threads in multi-threading processors  
A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the...
7418582 Versatile register file design for a multi-threaded processor utilizing different modes and register windows  
A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the...
7418584 Executing system management mode code as virtual machine guest  
In one embodiment, a register in a processor is programmable with an intercept indication indicative of whether or not an event that would cause a transition by the processor to a first mode is to...
7415383 Compiling method, apparatus, and program  
Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a...
7412591 Apparatus and method for switchable conditional execution in a VLIW processor  
An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and...
7406573 Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements  
A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor...
7395418 Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread  
A technique for improving the performance of a system that supports simultaneous multi-threading (SMT). When a first thread encounters a halt sequence, the system starts a transactional memory...
7395416 Computer processing system employing an instruction reorder buffer  
A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of...
7376819 Data processor with selectable word length  
An apparatus and method for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length)....
7363476 Method and apparatus to support an expanded register set  
According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing...
7360013 Method of rewriting flash EEPROM and electronic control device using same  
A method of rewriting a flash EEPROM of an electronic control device for controlling a vehicle equipment via a microcomputer is proposed. The flash EEPROM stores a control program and a flash...
7356647 Cache with integrated capability to write out entire cache  
A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register,...
7356670 Data processing system  
A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit ( 18 a ) and a...
7353368 Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support  
A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking...
7350060 Method and apparatus for sending thread-execution-state-sensitive supervisory commands to a simultaneous multi-threaded (SMT) processor  
A method and apparatus for sending thread-execution-state-sensitive supervisory commands to a simultaneous multi-threaded processor provides a mechanism for sending supervisory commands that must...
7350035 Information-processing apparatus and electronic equipment using thereof  
An information-processing apparatus comprises a motion-detecting unit, a motion-compensating unit, a DCT/IDCT unit, a Q/IQ unit, a VLC unit, a VLD unit, and a DSP unit, as a plurality of units. A...
7343480 Single cycle context switching by swapping a primary latch value and a selected secondary latch value in a register file  
A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to...
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