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7620798 |
Latency tolerant pipeline synchronization
A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction...
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7610451 |
Data transfer mechanism using unidirectional pull bus and push bus
A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory...
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7607042 |
Adjusting a processor operating parameter based on a performance criterion
Embodiments include a controller apparatus, a computerized apparatus, a device, an apparatus, and a method. A controller-apparatus includes a monitoring circuit for detecting a computational error...
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7603673 |
Method and system for reducing context switch times
An apparatus for managing resource in a multithreaded system, and attempting to increase the speed in which task switching occurs by controlling when thread state is stored to memory. The apparatus...
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7603566 |
Authenticated process switching on a microprocessor
A microprocessor includes a first information holding unit, a second information holding unit, and a switching authorization unit. The first information holding unit holds process identification...
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7600101 |
Multithreaded hardware systems and methods
Multithreaded hardware systems and methods are disclosed. One embodiment of a system may comprise a multithreaded processor comprising a register file having N hardware threads, where N is an...
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7596683 |
Switching processor threads during long latencies
In one embodiment, the present invention includes an apparatus to determine whether execution of an instruction of a first thread may require a long latency and switch to a second thread if the...
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7596682 |
Architected register file system utilizes status and control registers to control read/write operations between threads
An apparatus, a method, and a computer program are provided for an architected register file system for multithread system. In conventional architected register file systems, a thread is only...
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7590774 |
Method and system for efficient context swapping
Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location....
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7587585 |
Flag management in processors enabled for speculative execution of micro-operation traces
Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single...
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7587584 |
Mechanism to exploit synchronization overhead to improve multithreaded performance
Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a...
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7584346 |
Method and apparatus for supporting different modes of multi-threaded speculative execution
One embodiment of the present invention provides a system that supports different modes of multi-threaded speculative execution on a processor. The system starts with two or more threads executing...
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7577952 |
Common state sequences in a finite state machine
A state machine may have a sequence that is called by multiple threads within the state machine. Prior to calling the sequence, an address specific to the current state is stored in an address...
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7571318 |
Method and apparatus for improved security in a data processor
A method and apparatus for controlling access to segments of memory having security data stored therein is provided. A security check unit maintains information for a plurality of segments of...
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7571304 |
Generation of multiple checkpoints in a processor that supports speculative execution
One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for...
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7568089 |
Flag management in processors enabled for speculative execution of micro-operation traces
Managing speculative execution via groups of actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints...
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7562207 |
Deterministic microcontroller with context manager
A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the...
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7555631 |
RISC microprocessor architecture implementing multiple typed register sets
A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such...
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7552317 |
Methods and systems for grouping instructions using memory barrier instructions
Methods, systems, and articles of manufacture consistent with the present invention provide a memory instruction manager for managing the execution of instructions associated with a program. The...
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7549085 |
Method and apparatus to insert special instruction
A method and apparatus to insert special instruction. At least one of the illustrative embodiments is a method comprising converting a first representation of a computer program to a second...
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7546444 |
Register set used in multithreaded parallel processor architecture
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support...
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7543136 |
System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bits
One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The...
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7536690 |
Deferred task swapping in a multithreaded environment
A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has...
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7529916 |
Data processing apparatus and method for controlling access to registers
A data processing apparatus and method are provided for controlling access to registers. The data processing apparatus comprises a processing unit for performing data processing operations on data...
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7529915 |
Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source
Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch...
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7526636 |
Parallel multithread processor (PMT) with split contexts
The present invention relates to a parallel multithread processor ( 1 ) with split contexts, with M parallel-connected standard processor root units ( 2 ) being provided for instruction execution...
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7523455 |
Method and system for application managed context switching
A method for application managed CPU context switching. The method includes determining whether state data of a CPU is valid for a process. The determining is performed by the process itself. If...
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7516311 |
Deterministic microcontroller context arrangement
A method of operating a deterministic microcontroller is disclosed in which the microcontroller is switchable to various contexts. A plurality of sets of hardware registers is provided. A...
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7512773 |
Context switching using halt sequencing protocol
A halt sequencing protocol permits a context switch to occur in a processing pipeline even before all units of the processing pipeline are idle. The context switch method based on the halt...
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7503049 |
Information processing apparatus operable to switch operating systems
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed...
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7496921 |
Processing block with integrated light weight multi-threading support
A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various...
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7496896 |
Accessing return values and exceptions
One or more new methods are added to existing object code. The existing object code includes a first method that is capable of producing a result. New code is added to the first method. The new...
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7493621 |
Context switch data prefetching in multithreaded computer
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
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7493478 |
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft...
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7490228 |
Processor with register dirty bit tracking for efficient context switch
A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic...
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7490178 |
Threshold on unblocking a processing node that is blocked due data packet passing
A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the...
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7487339 |
Method and apparatus for binding shadow registers to vectored interrupts
A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and...
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7487335 |
Method and apparatus for accessing registers during deferred execution
One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order....
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7478394 |
Context-corrupting context switching
A virtual machine application interrupts execution of a host OS under software control at a predetermined interruption point, instead of interrupting the execution at an arbitrary instruction. The...
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7475230 |
Method and apparatus for performing register file checkpointing to support speculative execution within a processor
One embodiment of the present invention provides a system that performs register file checkpointing to support speculative execution within a processor. During operation, the system commences...
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7475229 |
Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit
In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store....
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7475224 |
Register map unit supporting mapping of multiple register specifier classes
Embodiments of this invention relate to sharing resources on a semiconductor between multiple functional units to reduce the number of register rename mappers and particularly to providing a way to...
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7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor
A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault...
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7469334 |
Method and apparatus for facilitating a fast restart after speculative execution
One embodiment of the present invention provides a system that facilitates a fast execution restart following speculative execution. During normal operation of the system, a processor executes code...
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7467289 |
Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited
Software can freeze portions of a pipeline operation in a processor by asserting a predetermined freeze register in the processor. The processor halts operations relating to portions of a common...
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7454600 |
Method and apparatus for assigning thread priority in a processor or the like
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further...
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7451296 |
Method and apparatus for pausing execution in a processor or the like
A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET...
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7444641 |
Context controller having context-specific event selection mechanism and processor employing the same
A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) an event recorder that records occurrences...
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7444500 |
Method for executing a 32-bit flat address program during a system management mode interrupt
A method and system for executing 32-bit flat address programs during a System Management Interrupt. The system provides a 16-bit SMI routine that is given control when an SMI occurs. That routine...
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7437724 |
Registers for data transfers
A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a...
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