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9032190 Recovering from an error in a fault tolerant computer system  
A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread...
9021239 Implementation of multi-tasking on a digital signal processor with a hardware stack  
The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack....
9015720 Efficient state transition among multiple programs on multi-threaded processors by executing cache priming program  
A system and method to optimize processor performance and minimizing average thread latency by selectively loading a cache when a program state, resources required for execution of a program or...
9015450 Apparatus utilizing efficient hardware implementation of shadow registers and method thereof  
Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming...
9009312 Controlling access to a resource in a distributed computing system with a distributed access request queue  
Controlling access to a resource in a distributed computing system that includes nodes having a status field, a next field, a source data buffer, and that are characterized by a unique node...
8972705 Executing instructions for managing constant pool base register used for accessing constants during subroutine execution  
A constant data accessing system having a constant pool comprises a computer processor having a constant pool base register, a compiler having a constant pool handler, and an instruction set...
8959317 Processor and method for saving designated registers in interrupt processing based on an interrupt factor  
A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which...
8949475 Efficient connection management in a SAS target  
A method includes pre-configuring a hardware-implemented front-end of a storage device with multiple contexts of respective connections conducted between one or more hosts and the storage device....
8949583 Concurrent atomic execution  
Executing a set one or more instructions is disclosed. A set of one or more register states is saved in a software data structure. The set of instructions is speculatively executed. At least one...
8898440 Request control device, request control method and associated processors  
A request control device, request control method, and a multiprocessor cooperation architecture. The request control device is connected to a request storage module and includes a comparing means...
8898438 Processor architecture for use in scheduling threads in response to communication activity  
The invention provides a processor comprising an execution unit for executing multiple threads, each thread comprising a sequence of instructions and each thread being designated to handle...
8893094 Hardware compilation and/or translation with fault detection and roll back functionality  
Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes...
8868887 Programmable event driven yield mechanism which may activate other threads  
Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a...
8856261 Network support for system initiated checkpoints  
A system, method and computer program product for supporting system initiated checkpoints in parallel computing systems. The system and method generates selective control signals to perform...
8850168 Processor apparatus and multithread processor apparatus  
A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which...
8850436 Opcode-specified predicatable warp post-synchronization  
One embodiment of the present invention sets forth a technique for performing a method for synchronizing divergent executing threads. The method includes receiving a plurality of instructions that...
8850169 Disabling threads in multithread environment  
A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for...
8832475 Programmable power mode sequencer  
A system includes a context file to store multiple contexts corresponding to different power modes of an electronic system, and a domain control device to generate control signals based, at least...
8826073 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits  
A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a...
8806181 Dynamic pipeline reconfiguration including changing a number of stages  
According to some embodiments, an apparatus having corresponding methods includes a storage module configured to store data and instructions; a first processor pipeline configured to process the...
8806180 Task execution and context switching in a scheduler  
A scheduler in a process of a computer system detects a task with an associated execution context that has not been previously invoked by the scheduler. The scheduler executes the task on a...
8799710 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits  
A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a...
8793433 Digital data processing apparatus having multi-level register file  
A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a...
8793474 Obtaining and releasing hardware threads without hypervisor involvement  
A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one...
8789042 Microprocessor system for virtual machine execution  
A processor includes guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. Root mode control registers...
8776079 Task processor  
A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective...
8762692 Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode  
Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements...
8751833 Data processing system  
A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing...
8719827 Processor and program execution method capable of efficient program execution  
A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a...
8707062 Method and apparatus for powered off processor core mode  
For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and...
8700883 Memory access techniques providing for override of a page table  
A memory access technique that provides for overriding a translation lookaside buffer and page table data structure, in accordance with one embodiment of the present invention, includes...
8694758 Mixing instructions with different register sizes  
When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent...
8688963 Checkpoint allocation in a speculative processor  
The embodiments described in the instant application provide a system for generating checkpoints. In the described embodiments, while speculatively executing instructions with one or more...
8689221 Speculative thread execution and asynchronous conflict events  
In an embodiment, asynchronous conflict events are received during a previous rollback period. Each of the asynchronous conflict events represent conflicts encountered by speculative execution of...
8683184 Multi context execution on a video processor  
A method for implementing multi context execution on a video processor having a scalar execution unit and a vector execution unit. The method includes allocating a first task to a vector execution...
8677105 Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines  
A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instructions formats includes a virtual register file, register cache and register file...
8677163 Context state management for processor feature sets  
Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The...
8671232 System and method for dynamically migrating stash transactions  
A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output...
8667256 Systems and method for managing divergent threads in a SIMD architecture  
One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The...
8661232 Register state saving and restoring  
In a data processing apparatus 1 having registers 6, when a state saving trigger event occurs while a result value of a data processing operation is still to be written to a destination register...
8656399 Runtime analysis and control method of folding indentified threads by assuming context of another thread and executing inlieu of another thread using thread folding tools  
A computer-implemented method of performing runtime analysis on and control of a multithreaded computer program. One embodiment of the present invention can include identifying threads of a...
8640008 Error recovery in a data processing apparatus  
A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error...
8635627 Method, medium and apparatus storing and restoring register context for fast context switching between tasks  
A method, medium and apparatus for storing and restoring a register context for a fast context switching between tasks is disclosed. The method, medium and apparatus may improve overall operating...
8631223 Register file supporting transactional processing  
A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register...
8631261 Context state management for processor feature sets  
Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The...
8626821 Limiting access to information corresponding to a context  
A device for limiting access to information corresponding to a context. The device has context logic configured to determine context and a trusted computing platform coupled to the context logic....
8621238 Using software-based decision procedures to control instruction-level execution  
An apparatus, method and program product are provided for securing a computer system. A digital signature of an application is checked, which is loaded into a memory of the computer system...
8601235 System and method for concurrently managing memory access requests  
A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a...
8589925 Techniques for switching threads within routines  
Various technologies and techniques are disclosed for switching threads within routines. A controller routine receives a request from an originating routine to execute a coroutine, and executes...
8578139 Checkpointing long latency instruction as fake branch in branch prediction mechanism  
A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions....