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8185722 |
Processor instruction set for controlling threads to respond to events
The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a...
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8181002 |
Merging checkpoints in an execute-ahead processor
One embodiment of the present invention provides a system that merges checkpoints on a processor. The system starts by executing instructions speculatively during a speculative-execution episode....
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8171268 |
Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectors
A technique for managing context state information enables a reduced number of save and restore operations. At least one embodiment includes a plurality of save area segments to store a plurality...
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8161273 |
Method and apparatus for programmatically rewinding a register inside a transaction
Embodiments of the present invention provide a system that allocates registers in a processor. The system starts by commencing a transaction, wherein commencing the transaction involves preserving...
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8151270 |
Method and apparatus for time-sliced and multi-threaded data processing in a communication system
A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to...
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8151268 |
Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads...
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8151095 |
System and method for context migration across CPU threads
One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique...
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8145884 |
Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor
A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first...
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8145471 |
Non-destructive simulation of a failure in a virtualization environment
A method for simulating a hardware failure in a virtualization environment includes determining a location of an instruction pointer for a particular operating system operating in the...
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8146093 |
Computer multiple operation system switching method
A computer multi-OS switching method, in which a data exchange region for storing OS running environment information is provided, wherein the method includes: A. saving running information of...
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8141098 |
Context switch data prefetching in multithreaded computer
An apparatus initiates, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known...
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8140834 |
System, method and computer program product for providing a programmable quiesce filtering register
A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor...
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8140825 |
Systems and methods for selectively closing pages in a memory
Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for...
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8140872 |
Restoring processor context in response to processor power-up
A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able...
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8136113 |
Method and apparatus for adjusting sleep time of fixed high-priority threads
A sleep function capable of putting a fixed high-priority thread to sleep within a time-window is disclosed. After a sleep request has been made by a fixed high-priority thread via the sleep...
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8131983 |
Method, apparatus and article of manufacture for timeout waits on locks
Embodiments of the invention provide techniques for performing timeout waits of process threads. Generally, a thread requesting access to locked resource sends a timeout request to a timeout...
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8122239 |
Method and apparatus for initializing a system configured in a programmable logic device
Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with...
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8108571 |
Multithreaded DMA controller
A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a...
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8108662 |
Checkpointing a hybrid architecture computing system
A method, apparatus, and program product checkpoint an application in a parallel computing system of the type that includes a plurality of hybrid nodes. Each hybrid node includes a host element and...
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8095782 |
Multiple simultaneous context architecture for rebalancing contexts on multithreaded processing cores upon a context change
Graphics processing elements are capable of processing multiple contexts simultaneously, reducing the need to perform time consuming context switches compared with processing a single context at a...
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8082426 |
Support of a plurality of graphic processing units
Included are systems and methods for supporting a plurality of Graphics Processing Units (GPUs). At least one embodiment of a system includes a context status register configured to send data...
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8082427 |
Multithread handling
A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for...
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8078854 |
Using register rename maps to facilitate precise exception semantics
One embodiment of the present invention provides a system that facilitates precise exception semantics. The system includes a processor that uses register rename maps to support out-of-order...
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8056088 |
Using scan chains for context switching
The invention sets forth an approach to context switching that utilizes scan chains modified to perform context switching operations. The design requires substantially less additional silicon area...
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8041754 |
Establishing thread priority in a processor or the like
In a multi-threaded processor, one or more variables are set up in memory (e.g., a register) to indicate which of a plurality of executable threads has a higher priority. Once the variable is set,...
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8041929 |
Techniques for hardware-assisted multi-threaded processing
Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing...
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8037476 |
Address level log-based synchronization of shared data
A method of address-level log-based synchronization comprises a thread attempting to acquire a lock on an object. If its lock attempt fails, a thread logs, at a synchronization log, data access...
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8032736 |
Methods, apparatus and articles of manufacture for regaining memory consistency after a trap via transactional memory
Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes...
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8027551 |
Reconfigurable image processor and the application architecture thereof
A reconfigurable image processor for image processing includes an arithmetic module, a first memory unit, a bus control module and a connecting module. By setting different configurations or...
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8028295 |
Apparatus, system, and method for persistent user-level thread
Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a...
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8024742 |
Common program for switching between operation systems is executed in context of the high priority operating system when invoked by the high priority OS
A method of enabling multiple different operating systems to run concurrently on the same computer, which is an Intel or similar Complex Instruction Set Computer architecture, comprising selecting...
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8024735 |
Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution
A system and method for determine which threads to execute at a given time in a multi-threaded computer system. A thread prioritizer determines execution fairness between pairs of potentially...
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8020169 |
Context switching system having context cache and a register file for the save and restore context operation
In an application in which context switching often occurs such as in a real time OS, it is possible to significantly reduce the overhead caused by the context switching. The OS issues a Swap...
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8019978 |
Unit status reporting protocol
A unit status reporting protocol may also be used for context switching, debugging, and removing deadlock conditions in a processing unit. A processing unit is in one of five states: empty, active,...
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8019973 |
Information processing apparatus and method of controlling register
An information processing apparatus and a method of controlling the same that employs a register window system and a Simultaneous Multithreading method for reducing circuit areas by sharing a data...
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8015568 |
Disk drive/CPU architecture for distributed computing
A disk drive is described which executes distributed computing tasks including a CPU and associated memory. The communication interface with the host computer is modified to allow the host computer...
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8010773 |
Hardware constrained software execution
Restricting execution by a computing device of instructions within an application program. The application program is modified such that execution of the selected instructions is dependent upon a...
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8006076 |
Processor and program execution method capable of efficient program execution
A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a...
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8006247 |
Multi-tasking real-time operating system for microprocessors with limited memory
A real-time operating system (RTOS) for use with minimal-memory controllers has a kernel for managing task execution, including context switching, a plurality of defined tasks, individual ones of...
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8001549 |
Multithreaded computer system and multithread execution control method
A multithreaded computer system of the present invention includes a plurality of processor elements (PEs) and a parallel processor controller which switches threads in each PE. The parallel...
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7996663 |
Saving and restoring architectural state for processor cores
A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing element, such as a core, is...
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7996659 |
Microprocessor instruction that allows system routine calls and returns from all contexts
An apparatus comprises register means for storing a return context upon initiation of a supervisor call instruction and restoring means to restore a privilege level and status register upon...
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7991983 |
Register set used in multithreaded parallel processor architecture
A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple...
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7987346 |
Method and apparatus for assigning thread priority in a processor or the like
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further...
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7984438 |
Virtual machine transitioning from emulating mode to enlightened mode
A computing device has a hardware device employed to provide a hardware service to the computing device and a plurality of virtual machines including a host virtual machine (VM-H) to which the...
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7984352 |
Saving debugging contexts with periodic built-in self-test execution
A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic...
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7979680 |
Multi-threaded parallel processor methods and apparatus
A processor system may implement multiple contexts on one or more processors having a local memory. Code and/or data for first and second contexts may be respectively stored simultaneously in first...
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7979783 |
Error detection device and method for error detection for a command decoder
An error detection device for a command decoder is described, the command decoder reading out an associated sequence of control signal words from a command memory based on an input word, wherein...
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7979684 |
Method and context switch device for implementing design-for-testability functionality of latch-based register files
A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a...
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7971041 |
Method and system for register management
A system and method of allocating registers in a register array to multiple workloads is disclosed. The method identifies an incoming workload as belonging to a first process group or a second...
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