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9043580 Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)  
A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor...
9043584 Generating hardware events via the instruction stream for microprocessor verification  
A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event...
9032190 Recovering from an error in a fault tolerant computer system  
A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread...
8984263 Information processing device and emulation processing program and method  
An emulation processing method causing a computer including a first and a second processor to execute emulation processing, the emulation processing method includes: calculate a next instruction...
8972704 Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory  
A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by...
8959339 Method and system for preventing unauthorized processor mode switches  
A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple...
8954714 Processor with cycle offsets and delay lines to allow scheduling of instructions through time  
An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than...
8943248 Method and system for handling discarded and merged events when monitoring a system bus  
A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. The bus is...
8930683 Memory order tester for multi-threaded programs  
One method of testing multi-threaded code involves accessing a first set of instructions which are configured to be executed, in execution order, as a thread of a multi-threaded process. A memory...
8924634 Method for performing host-directed operations, and associated memory device and controller thereof  
A method for performing host-directed operations is provided, where the method is applied to a controller of a Flash memory that includes a plurality of blocks. The method includes: in a test mode...
8914621 Processing unit that detects manipulations thereof, device comprising two processing units, method for testing a processing unit and a device comprising two processing units  
A processing unit having a control unit configured to execute after a reset phase a sequence of test instructions to detect a manipulation of the processing unit before the control unit decodes a...
8898051 System and method for implementing a trace interface  
A system and method for selectively capturing and storing emulation data results from a hardware emulation system, which reduces the data bandwidth requirement and the unnecessary consumption of...
8891757 Programmable cryptographic integrated circuit  
A cryptographic integrated circuit including a programmable main processor for executing cryptographic functions, an internal memory, and a data transmission bus to which the main processor and...
8874837 Embedded memory and dedicated processor structure within an integrated circuit  
An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random...
8874883 Debugging of a data processing apparatus  
A data processing apparatus is provided comprising processing circuitry and instruction decoding circuitry. The data processing apparatus is capable of operating at a plurality of different...
8874965 Controlling program code execution shared among a plurality of processors  
The present invention enables program codes to be shared among processors 211. To prevent the debug operation of one processor 211 from affecting the debug operation of the other processors 211,...
8832416 Method and apparatus for instruction completion stall identification in an information handling system  
An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes...
8826234 Relational modeling for performance analysis of multi-core processors  
A relational model may be used to encode primitives for each of a plurality of threads in a multi-core processor. The primitives may include tasks and parameters, such as buffers. The...
8806505 Service and project request processing within a business enterprise  
A system and method for request processing management that includes receiving requests for tasks from a plurality of sources; reviewing the requests by a review group comprising representatives...
8806178 Set sampling controls instruction  
A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the...
8788796 Technique for simulating floating-point stack operation involving conversion of certain floating-point register numbers based on a top-of-stack pointer and modulo function  
A Reduced Instruction Set Computing (RISC) processor is capable of emulating operation of a floating-point register stack. The RISC processor may include a floating-point register file containing...
8775840 Virtualization in a multi-core processor (MCP)  
This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The...
8751772 Methods and apparatus for scalable array processor interrupt detection and response  
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
8745361 Sandboxed execution of plug-ins  
A sandbox architecture that isolates and identifies misbehaving plug-ins (intentional or unintentional) to prevent system interruptions and failure. Based on plug-in errors, the architecture...
8732443 Program processing device and program processing method which is able to control writing into an internal memory  
A program processing device comprises a CPU for carrying out predetermined processing according to a program; an internal memory storing the program and data generated by the CPU by carrying out...
8719556 System and method for performing deterministic processing  
A system and method is provided for performing deterministic processing on a non-deterministic computer system. In one example, the system forces execution of one or more computer instructions to...
8713371 Controlling generation of debug exceptions  
A data processing apparatus for performing data processing operations in response to execution of program instructions and debug circuitry for performing operations. The data processing apparatus...
8706937 Method and system of debugging multicore bus transaction problems  
A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are...
8700955 Multi-processor data processing system having synchronized exit from debug mode and method therefor  
A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for...
8694757 Tracing command execution in a parallel processing system  
Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing...
8689223 Mechanisms to detect priority inversion  
A method, computer program product, and device are provided for detecting and identifying priority inversion. A higher priority thread and a lower priority thread are received. A debugging...
8689180 Systems and methods for resource leak detection  
Systems and methods for detecting resource leaks in a program using static analysis are disclosed. Dynamically adjustable sets of must-access paths can be employed for aliasing purposes to track...
8677104 System for efficiently tracing data in a data processing system  
A data processing apparatus is provided comprising prediction circuitry for predicting a response of the data processing circuitry at at least one given execution point to execution of a program...
8667255 Measuring runtime coverage of architectural events of a microprocessor  
A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all...
8661231 Multi-function instruction that determines whether functions are installed on a system  
A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or...
8656375 Cross-logical entity accelerators  
A cross-logical entity group is created that includes one or more accelerators to be shared by a plurality of logical entities. Instantiated on the accelerators are functions that are common...
8656366 Microprogrammable device code tracing with single pin transmission of execution event encoded signal and trace memory storing instructions at same address  
A microprogrammable electronic device has a first code memory storing instructions, and is configured to execute each instruction in the first code memory at a respective instruction cycle. The...
8645759 Debugging mechanism having an OR circuit for triggering storage of arithmetic operation data whenever a valid control signal is received or a clock-based counter overflows  
A debugging mechanism receives arithmetic operation data inputs for causing an arithmetic unit to perform an arithmetic operation, and a control signal used for the arithmetic operation. The...
8639919 Tracer configuration and enablement by reset microcode  
A microprocessor is provided with a reset logic flag and corresponding reset microcode that selectively enables the reset microcode to set up and enable debug logic before the microprocessor...
8635435 Method for monitoring a cyclic user program  
There is described a method for monitoring a cyclic user program which is executed on an automation device by means of a programming device connected to communicate with the automation device,...
8635436 Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall  
During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish...
8631160 Development of parallel/distributed applications  
One embodiment of the present invention provides a method for supporting the development of a parallel/distributed application, wherein the development process comprises a design phase, an...
8626074 Method for controlling a control station for determining a bandwidth for data communication  
A method for controlling a control station (H1) includes the steps of performing wireless connection processing (204) with a terminal station (D1) and when a wireless connection is established,...
8627049 Real-time prioritization of stall or event information  
Disclosed herein is a system and method for executing a series of instructions on a circuit. The system comprises an encoder that receives event data corresponding to the executed instructions....
8627050 Executing perform floating point operation instructions  
A method and system are disclosed for executing a machine instruction in a central processing unit. The method comprise the steps of obtaining a perform floating-point operation instruction;...
8615619 Qualifying collection of performance monitoring events by types of interrupt when interrupt occurs  
A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring...
8612730 Hardware assist thread for dynamic performance profiling  
A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The...
8601324 Storage and output of trace data  
A trace output unit for collecting, buffering and outputting trace data generated by trace circuitry monitoring processing activities of a data processing apparatus is described. The trace output...
8595389 Distributed performance counters  
A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data...
8595472 Ganged hardware counters for coordinated rollover and reset operations  
Mechanisms for controlling rollover or reset of hardware performance counters in the data processing system. A signal indicating that a rollover or reset of a first hardware performance counter...