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7624256 |
System and method wherein conditional instructions unconditionally provide output
A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not...
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7624251 |
Instructions for efficiently accessing unaligned partial vectors
One embodiment of the present invention provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch...
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7620800 |
Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions
Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including...
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7620797 |
Instructions for efficiently accessing unaligned vectors
One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is...
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7617334 |
Data processing system, data processing method and program
In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and...
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7600221 |
Methods and apparatus of an architecture supporting execution of instructions in parallel
A processing architecture supports executing instructions in parallel after identifying at least one level of dependency associated with a set of traces within a segment of code. Each trace...
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7596680 |
System and method for encoding and decoding architecture registers
A system and method to extend the number of architecturally visible registers in a processor while preserving the number of bits of the instruction encoding. The system comprises: an indirection...
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7590829 |
Extension adapter
A processor system. The processor system comprises a processor having a first set of instructions associated therewith. The processor system also comprises a programmable logic device and an...
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7587583 |
Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode
Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or performing a task assigned to the Java WIDE...
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7581037 |
Effecting a processor operating mode change to execute device code
Provided are a method, system and program for effecting a processor operating mode change to execute device code. A processor receives a call while the processor is operating in a first mode,...
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7568055 |
Data processing apparatus for selecting either a PIO data transfer method or a DMA data transfer method
The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit...
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7561930 |
Dynamic modifier function blocks for use in a process control system
Dynamic modifier function blocks for use in a process control system are disclosed. In accordance with one aspect, an example function block is stored on a machine readable medium for use in a...
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7559061 |
Simultaneous multi-threading control monitor
One example would provide for maximum throughput thus increasing capacity during times when only low and medium priority work is running while allowing for the shorter turn around times required by...
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7543287 |
Using a block device interface to invoke device controller functionality
In one embodiment, a standard block device command is received at a device controller. The standard block device command is addressed to a virtual block device associated with the device...
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7543135 |
Processor and method for selectively processing instruction to be read using instruction code already in pipeline or already stored in prefetch buffer
There is provided a processor including: an instruction pipeline pipeline-processing an instruction code; a comparison unit that compares an instruction code in the instruction pipeline or in an...
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7536229 |
Information processing apparatus, information processing method, and computer program
An information processing apparatus includes a first information processor, a plurality of second information processor, and a plurality of temperature detecting units detecting temperature in the...
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7533250 |
Automatic operand load, modify and store
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode...
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7530072 |
Method to segregate suspicious threads in a hosted environment to prevent CPU resource exhaustion from hung threads
A system and method for segregating suspicious threads in a hosted environment to prevent CPU resource exhaustion from hung threads are disclosed. An application server identify suspicious threads...
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7526638 |
Hardware alteration of instructions in a microcode routine
Processor logic gates are used to modify microcode instructions, while they are being executed. The results of previous operations are used by the hardware to modify subsequent instructions in a...
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7509365 |
Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which...
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7502918 |
Method and system for data dependent performance increment and power reduction
A method of dispatching instructions includes dispatching original instructions into an instruction buffer, including at least one operand, renaming the operand, selecting the original instructions...
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7500086 |
Start transactional execution (STE) instruction to support transactional program execution
One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally....
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7496656 |
Processing instruction words
A method for processing an instruction word in a data processing system, the instruction word comprising a plurality of instruction bit positions, each bit position corresponding to an instruction...
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7487338 |
Data processor for modifying and executing operation of instruction code according to the indication of other instruction code
A MOD_SAT instruction indicating that a 16 bit saturation is to be carried out with respect to the operation of one of instructions executed in parallel is placed in the left container and an ADD...
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7480771 |
Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged
We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated,...
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7458078 |
Apparatus and method for autonomic hardware assisted thread stack tracking
Method and apparatus for tracking thread stacks during a trace of a computer program. Hardware assistance mechanisms allow a processor to autonomically maintain a thread work area for each thread...
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7451297 |
Computing system and method that determines current configuration dependent on operand input from another configuration
A dataflow graph is split into sub-graphs referred to as configurations, each configuration comprising computational hardware containing elements that operate on operand sets. A configuration...
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7447877 |
Method and apparatus for converting memory instructions to prefetch operations during a thread switch window
A method and apparatus for converting memory instructions to prefetch operations during a thread switch window is disclosed. In one embodiment, memory access instructions that are already inside an...
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7447867 |
Non-intrusive address mapping having a modified address space identifier and circuitry therefor
A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space...
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7434035 |
Method and system for processing instructions in grouped and non-grouped modes
An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor...
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7434004 |
Prefetch prediction
Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution...
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7418579 |
Component with a dynamically reconfigurable architecture
The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through...
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7418575 |
Long instruction word processing with instruction extensions
A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of...
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7415601 |
Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters
A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for...
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7415599 |
Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location
A repeat instruction (RPT) operates on one or more operands, but the RPT instruction includes only an opcode and does not specify locations of the operand or operands. The type of operation to be...
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7409534 |
Automatic and transparent hardware conversion of traditional control flow to predicates
A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a...
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7406573 |
Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements
A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor...
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7404181 |
Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold
A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first...
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7401204 |
Parallel Processor efficiently executing variable instruction word
A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information....
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7389405 |
Digital signal processor architecture with optimized memory access for code discontinuity
A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code...
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7386708 |
Secure hardware personalization service
Methods and devices for securely providing personalities to reconfigurable hardware. Reconfigurable hardware is provided with one or more domains. At least one domain serves as a gatekeeper domain...
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7380103 |
Apparatus and method for selective control of results write back
A microprocessor apparatus and method are provided, for selectively controlling write back of a result. The apparatus includes translation logic and extended execution logic. The translation logic...
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7376818 |
Program translator and processor
Multiple instructions, specifying equivalent operations but designating different execution units, are stored beforehand on an instruction exchange table. First, a primary compiler compiles a...
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7370123 |
Information processing apparatus
A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address...
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7363620 |
Non-linear execution of application program instructions for application program obfuscation
Obfuscating an application program comprises reading a first application program, determining an application program instruction location permutation that transforms the first application program...
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7363473 |
System for dynamic service provisioning
Disclosed is a network processor configured to provide for dynamic service provisioning. A global connector defines a topology of packet processing functions that can be dynamically ordered to...
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7360068 |
Reconfigurable signal processing IC with an embedded flash memory device
A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field...
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7360028 |
Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol
A method and apparatus for performing a store-to-instruction-space instruction are provided. A unique opcode indicates that a data value is to be written to an instruction space in main memory. The...
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7346762 |
Replacing instruction and corresponding instructions in a queue according to rules when shared data buffer is accessed
A method of executing program instructions may include receiving, in a processor, an instruction that causes the processor to read data from or write data to a portion of memory that is shared by...
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7340592 |
Executing a translated block of instructions and branching to correction code when expected top of stack does not match actual top of stack to adjust stack at execution time to continue executing without restarting translating
A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a...
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