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9032189 Efficient conditional ALU instruction in read-port limited register file microprocessor  
A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a...
9021454 Operand and limits optimization for binary translation system  
Methods and systems for optimizing generation of natively executable code from non-native binary code are disclosed. One method includes receiving a source file including binary code configured...
RE45458 Dual function system and method for shuffling packed data elements  
An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data...
8984262 Generate predicates instruction for processing vectors  
The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a first input vector, a second input vector, and optionally receiving a...
8966461 Vector width-aware synchronization-elision for vector processors  
A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent...
8959316 Actual instruction and actual-fault instructions for processing vectors  
The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a vector instruction that optionally receives a predicate vector (which has N...
8938072 Cryptographic key derivation device and method therefor  
A data processing system includes a cryptographic processing module providing for cryptographic key generation. A method entails computing derived keys one time, during a first execution of a key...
8924695 Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor  
An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if...
8893095 Methods for generating code for an architecture encoding an extended register specification  
There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width...
8893104 Method and apparatus for register spill minimization  
The aspects enable a computing device to allocate memory space to variables during runtime compilation of a software application. A compiler may be modified to identify operations that can be...
8893094 Hardware compilation and/or translation with fault detection and roll back functionality  
Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes...
8893079 Methods for generating code for an architecture encoding an extended register specification  
There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width...
8892851 Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions  
A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second...
8880846 Semiconductor device  
A semiconductor device according to the present invention includes a first address generation unit that includes a first register group and generates a table address by a cyclically repeating...
8880857 Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor  
A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an...
8874882 Compiler-directed sign/zero extension of a first bit size result to overwrite incorrect data before subsequent processing involving the result within an architecture supporting larger second bit size values  
Apparatus and methods to add an extended first bit size data item of a first source operand specified by an instruction to a second source operand specified by the instruction. The first source...
8819399 Predicated control flow and store instructions for native code module security  
Some embodiments provide a system that executes a native code module. During operation, the system obtains the native code module. Next, the system loads the native code module into a secure...
8788795 Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors  
A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is...
8788796 Technique for simulating floating-point stack operation involving conversion of certain floating-point register numbers based on a top-of-stack pointer and modulo function  
A Reduced Instruction Set Computing (RISC) processor is capable of emulating operation of a floating-point register stack. The RISC processor may include a floating-point register file containing...
8781613 Audio apparatus for portable devices  
An audio apparatus for a portable device is provided. The portable device includes computing hardware coupled to associated data memory, which stores one or more audio or computer program products...
8738892 Very long instruction word (VLIW) computer having efficient instruction code format  
A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a...
8732442 Method and system for hardware-based security of object references  
A method for managing data, including obtaining a first instruction for moving a first data item from a first source to a first destination, determining a data type of the first data item,...
8717586 Image processing apparatus that performs processing according to instruction defining the processing, control method for the apparatus, and storage medium  
An image processing apparatus which makes it possible to select a plurality of instructions at a time, and connect a plurality of documents together so that they can be processed as one document....
8713292 Reducing energy and increasing speed by an instruction substituting subsequent instructions with specific function instruction  
A data processing system is used to evaluate a data processing function by executing a sequence of program instructions including an intermediate value generating instruction and an intermediate...
8677106 Unanimous branch instructions in a parallel thread processor  
One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed,...
8635434 Mathematical operation processing apparatus for performing high speed mathematical operations  
A mathematical operation processing apparatus is disclosed by which the supply of an operand which is performed based on condition codes by a plurality of mathematical operations can be performed...
8615646 Unanimous branch instructions in a parallel thread processor  
One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed,...
8601244 Apparatus and method for generating VLIW, and processor and method for processing VLIW  
An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein....
8601245 Not-taken path instruction for selectively generating a forwarded result from a previous instruction based on branch outcome  
A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field...
8595712 Source code processing method, system and program  
A method, system, and computer readable article of manufacture to enable parallel execution of a divided source code in a multiprocessor system. The method includes the steps of: inputting an...
8589664 Program flow control  
A data processing apparatus includes a data engine 6 having an instruction decoder 18 for generating one or more control signals 24 for controlling processing circuitry 20 to perform data...
8584109 Virtualization for diversified tamper resistance  
A computer-implementable method includes providing an instruction set architecture that comprises features to generate diverse copies of a program, using the instruction set architecture to...
8572357 Monitoring events and incrementing counters associated therewith absent taking an interrupt  
A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is...
8549266 System and method of instruction modification  
A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the...
8495354 Apparatus for determining during a power-on sequence, a value to be written to a first register in a secure area and the same value to a second register in non-secure area, which during a protected mode, the value is compared such that if it is equal, enabling writing to a memory  
Systems and methods of securely updating BIOS are disclosed. One such system comprises a reprogrammable memory, a first and a second register, and comparison logic. The reprogrammable memory...
8489858 Methods and apparatus for scalable array processor interrupt detection and response  
Hardware and software techniques for interrupt detection and response are provided in a scalable pipelined array processor environment. Utilizing these techniques, a sequential program execution...
8489867 Monitoring events and incrementing counters associated therewith absent taking an interrupt  
A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is...
8478976 System and method of automated function activation for electronic devices  
A system and method of storing a default function from among possible functions to be executed by a device, and executing the default function after a pre-defined interval, if during the interval...
8458414 Accessing memory with identical instruction types and central processing unit thereof  
A memory accessing method including the following steps is provided. Firstly, two instructions are fetched. Next, the two instructions are respectively decoded to obtain two operation fields and...
8447958 Substituting portion of template instruction parameter with selected virtual instruction parameter  
A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to...
8443171 Run-time updating of prediction hint instructions  
The present invention provides a system and method for runtime updating of hints in program instructions. The invention also provides for programs of instructions that include hint performance...
8429638 Instruction exploitation through loader late fix-up  
A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate...
8423748 Register control circuit and register control method  
A register control circuit that controls a register specified by an inputted address includes a signal output that outputs a first control signal and a second control signal based on the inputted...
8407679 Source code processing method, system and program  
A method, system, and computer readable article of manufacture to enable parallel execution of a divided source code in a multiprocessor system. The method includes the steps of: inputting an...
8402251 Selecting configuration memory address for execution circuit conditionally based on input address or computation result of preceding execution circuit as address  
A semiconductor device includes a first circuit that executes a first calculation, a second circuit that includes a first storage unit therein and executes a second calculation, a controller that...
8402256 Processing prefix code in instruction queue storing fetched sets of plural instructions in superscalar processor  
The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an...
8386747 Processor and method for dynamic and selective alteration of address translation  
Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit...
8381040 Relocatable interrupt handler for test generation and execution  
A relocatable interrupt handler for use in test generation and execution. A method for executing test code includes executing a test code block that includes a plurality of test instructions. The...
8356165 Selecting regions of hot code in a dynamic binary rewriter  
An approach to region selection which extends beyond traces and selects super-regions. A super-region (SR) contains arbitrary control flow, such as interprocedural nested loops, that provides a...
8356162 Execution unit with data dependent conditional write instructions  
An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional...