Matches 201 - 250 out of 358 < 1 2 3 4 5 6 7 8 >
Match Document Document Title
6216221 Method and apparatus for expanding instructions  
A microprocessor includes a decoder, a queue, and a renamer. The decoder is adapted to receive a program instruction and decode the program instruction to provide a first decoded instruction. The...
6212628 Mesh connected computer  
An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a...
6209082 Apparatus and method for optimizing execution of push all/pop all instructions  
An apparatus and method are provided for executing a push all/pop all instruction in a pipeline microprocessor. The apparatus includes an instruction buffer and a translator. The instruction buffer...
6205546 Computer system having a multi-pointer branch instruction and method  
A computer and a method are described having multiple pointers for a branch instruction. A branch target instruction called by the branch instruction is divided into H parts locatable by K...
6202144 Computer system having a single pointer branch instruction and method  
A computer system and method are described having a single pointer for a branch target instruction and multiple pointers and instruction parts for non-branch target instructions. All instructions,...
6199156 System for explicitly referencing a register for its current content when performing processor context switch  
In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be...
6185672 Method and apparatus for instruction queue compression  
A microprocessor having an instruction queue capable of out-of-order instruction dispatch and compaction of unaligned strings of empty storage locations is disclosed. The microprocessor may...
6183141 Minimizing program code storage for performing regular and repetitive operations in a programmable processor  
The program memory comprises a first segment (MP1) containing a succession of program words including first base words (MMA) each having a size less than the sum of the respective sizes of the...
6173394 Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result  
A data processing apparatus includes plural data registers, an arithmetic logic unit and a status register. The status register stores a plurality of different types of status bits. These status...
6170052 Method and apparatus for implementing predicated sequences in a processor with renaming  
Systems, apparatus, and methods are disclosed for generating pairs of conditional instructions corresponding to special predicate sequences from single instructions having a predicate. These pairs...
6164840 Ensuring consistency of an instruction cache with a store cache check and an execution blocking flush instruction in an instruction queue  
A method of ensuring instruction cache consistency in a processor includes executing a flush instruction whenever a program executed by the processor stores data to a given data address and,...
6167461 Programmable high performance disk formatter for headerless disk drive controller executing a series of low level instructions generated by a high level processing engine  
A programmable disk formatter for a disk controller in a headerless hard disk drive (HDD) system is disclosed. The disk formatter includes a high level processing engine that generates on the fly...
6167507 Apparatus and method for floating point exchange dispatch with reduced latency  
A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction....
6161174 Pipelined central processor incorporating indicator busy sensing and responsive pipeline timing modification  
A pipelined processor for simultaneously performs one of a plurality of successive operations on each of a plurality of successive instructions within the pipeline, the successive operations...
6157997 Processor and information processing apparatus with a reconfigurable circuit  
Part or all of an instruction decoder is constructed of a first reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal. Further, a second...
6145075 Apparatus and method for executing a single-cycle exchange instruction to exchange contents of two locations in a register file  
An apparatus and method for exchanging operands within a microprocessor is provided. The apparatus contains a translator for generating a micro instruction that loads a first operand into a second...
6128720 Distributed processing array with component processors performing customized interpretation of instructions  
A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. Each of the processors in...
6125442 Method, system and data structures for computer software application development and execution  
A method, system and data structures for software development and execution includes a Run Time Event Manager and a set of Models. A Model is a type of data structure that contains no code but an...
6122730 "Test under mask high" instruction and "Test under mask low" instruction executing method and apparatus  
An arithmetic method and apparatus for executing a TMH (Test under Mask High) and a TML (Test under Mask Low) instruction. This apparatus comprises a circuit for detecting that the result of an AND...
6094718 Programmable controller with a BPU that executes first-class instructions, a CPU that executes second-class instructions, and a skip instruction processing section that skips the current instruction without transferring control right to CPU  
A programmable controller includes a BPU that executes first-class instructions, a CPU that executes second-class instructions, and a memory that is shared by the BPU and the CPU and stores a...
6092185 Opcode compare logic in E-unit for breaking infinite loops, detecting invalid opcodes and other exception checking  
A computer processor which has an apparatus in its Execution Unit (E-unit) that detects a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer...
6086623 Method and implementation for intercepting and processing system calls in programmed digital computer to emulate retrograde operating system  
A current operating system such as Solaris® X86 is adapted to run a user program such as a Common Object File Format (COFF) executable program which was designed to run on a retrograde operating...
6085308 Protocol processor for the execution of a collection of instructions in a reduced number of operations  
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor...
6076156 Instruction redefinition using model specific registers  
A microprocessor employs an instruction redefinition register which programmably redefines the operation performed by one or more instructions. Instructions may be added to the instruction set...
6058473 Memory store from a register pair conditional upon a selected status bit  
A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store...
6041399 VLIW system with predicated instruction execution for individual instruction fields  
In the case of constituting a processing unit having the characteristic of a VLIW type processing unit and the characteristic of a pipeline type processing unit, since reference to the result of...
6041404 Dual function system and method for shuffling packed data elements  
An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data...
6038659 Method for using read-only memory to generate controls for microprocessor  
A circuit for generating control signals used in a microprocessor has a storage array, such as a read-only memory (ROM) array, which contains a plurality of predefined logic patterns. An entry of...
6035391 Floating point operation system which determines an exchange instruction and updates a reference table which maps logical registers to physical registers  
A system for processing a floating point instruction includes a stack, virtual registers, a stack pointer pointing to one of the virtual registers as top of stack, physical registers, and a...
6035390 Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation  
A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that...
6029004 Method and apparatus for modular reordering of portions of a computer program based on profile data  
An apparatus and method reorder portions of a computer program in a way that achieves both enhanced performance and maintainability of the computer program. A global call graph is initially...
6026484 Data processing apparatus, system and method for if, then, else operation using write priority  
A data processing apparatus employs write priority to permit a data processing apparatus to execute an if, then, else operation in a single instruction cycle. The data processing apparatus includes...
6026481 Microprocessor with distributed registers accessible by programmable logic device  
A chip includes a programmable logic device and a microprocessor, wherein at least one of the associated registers of the microprocessor is distributed in the programmable logic device. The...
6026485 Instruction folding for a stack-based machine  
An instruction decoder allows the folding away of JAVA virtual machine instructions pushing an operand onto the top of a stack merely as a precursor to a second JAVA virtual machine instruction...
6023758 Method and processor for changing program by replacing instruction stored in ROM with predetermined value to be interpreted as an instruction  
According to the present invention, a method for changing a program including a plurality of instructions in a processor having a ROM for storing the program therein is provided. The method...
6016544 Apparatus and method for tracking changes in address size and for different size retranslate second instruction with an indicator from address size  
An apparatus and method for improving the execution speed of stack segment load operations is provided. Rather than delaying translation of instructions following stack segment loads, until the...
6014736 Apparatus and method for improved floating point exchange  
A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes...
6012140 Processing system, processing unit, memory and compiling method  
A processor contains a memory and a processing unit. The memory is of a type which loses data upon reading. The processing unit has instructions of a first type and of a second type, each of which,...
6009512 Mechanism for forwarding operands based on predicated instructions  
A method and apparatus for providing predicated instructions in a processor employing out of order execution. In one embodiment, a plurality of decode units are configured to decode a plurality of...
6009273 Method for conversion of a variable argument routine to a fixed argument routine  
A compiler method analyzes a program listing to identify a first set of subroutines therein, each of which accepts a variable number of arguments, converting the first set of subroutines into...
5999860 Method and apparatus for optimizing digital processing  
A method and apparatus for optimizing digital processing in a computer system is accomplished when at least one of a plurality of digital processing operations (i.e., a set of programming...
6000028 Means and apparatus for maintaining condition codes in an unevaluated state  
A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer...
5983337 Apparatus and method for patching an instruction by providing a substitute instruction or instructions from an external memory responsive to detecting an opcode of the instruction  
A superscalar microprocessor implements instruction level patching. A instruction fetch unit includes a register for storing opcodes of instructions to be patched. When an instruction is fetched,...
5961615 Method and apparatus for queuing data  
A queue structure includes a plurality of entries, a plurality of ports coupled to the entries, a plurality of enable lines coupled to the entries and the ports, and control logic. Each enable line...
5956494 Method, apparatus, and computer instruction for enabling gain control in a digital signal processor  
A digital signal processor (10) for implementing a gain instruction. The gain instruction, when decoded, controls a multiplexer (43) to select a gain control index signal. The value of the chosen...
5948097 Method and apparatus for changing privilege levels in a computer system without use of a call gate  
A method and apparatus for performing a system call in a system having a user privilege level and a kernel privilege level, wherein the kernel privilege level is higher than the user privilege...
5948098 Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines  
A CPU (central processing unit) of a computer that comprises an issue unit and an execution unit. The issue unit selectively issues arithmetic instructions of a predefined arithmetic instruction...
5946483 Devices, systems and methods for conditional instructions  
A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to...
5942983 Assuring data read/write operation in an electronic appliance  
In a communication system, when data is read/written from/into a memory contained in a recording medium employed in one electronic appliance by another electronic appliance via a communication...
5931939 Read crossbar elimination in a VLIW processor  
In a VLIW processor that has an instruction issue register, functional units, and a multiport register file, a portion or all of the read crossbar is eliminated.
Matches 201 - 250 out of 358 < 1 2 3 4 5 6 7 8 >