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6647489 Compare branch instruction pairing within a single integer pipeline  
An apparatus and method are provided for executing a combined compare-and-branch operation in a single integer pipeline microprocessor. Typically, the compare-and-branch operation is specified by...
6637026 Instruction reducing predicate copy  
When compiling software for a processor that supports predication, an alerting instruction can be inserted to alert a global register allocator to map particular virtual predicates into the same...
6629235 Condition code register architecture for supporting multiple execution units  
A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated...
6615333 Data processing device, method of executing a program and method of compiling  
A data processing device has a circuit for correcting an effect of executing memory access instructions out of order with respect to one another in a pipeline. A detector detects whether a same...
6611909 Method and apparatus for dynamically translating program instructions to microcode instructions  
In a computer system the instruction decoding unit for translating program instructions to microcode instructions operates dynamically. Thus the unit receives state signals indicating the state of...
6606703 Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions  
Processor and instruction conversion apparatus, including a technique for reducing the number of types of instructions and processor hardware scale when conditional instructions are used. The...
6604192 System and method for utilizing instruction attributes to detect data hazards  
A computer system utilizing a processing system capable of efficiently comparing register identifiers and instruction attribute data to detect data hazards between instructions of a computer...
6591344 Method and system for an INUSE field resource management scheme  
A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read...
6574728 Condition code stack architecture systems and methods  
A computer system includes a register file and an arithmetic logic unit (ALU) for reading data from the register file. The ALU is configured to conduct data processing of the data which was and to...
6571329 Detection of overwrite modification by preceding instruction possibility of fetched instruction code using fetched instructions counter and store target address  
The present invention aims at improving the performance of the process of an information processing apparatus which includes an instruction fetch port, and can detect the possibility for the...
6564316 Method and apparatus for reducing code size by executing no operation instructions that are not explicitly included in code using programmable delay slots  
There is disclosed a state machine made up of a delay slot path and a no operation path, both made up of nodes with arcs connecting between them. There are arcs between the nodes of the delay slot...
6550005 Mechanism for recovery from termination of a program instruction due to an exception in a pipeland processing system  
Apparatus ( 5 ) and method for processing data in response to a sequence of program instructions including a primary pipelined processing unit ( 40 ) for performing data processing, the primary...
6542985 Event counter  
A data processor is disclosed that executes a number of microcode instruction words. Each of the microcode instruction words has a bit field reserved to indicate which, if any, event counters are...
6526572 Mechanism for software register renaming and load speculation in an optimizer  
The inventive mechanism operates to optimize program efficiency in a two phase process. In the first phase, the mechanism conducts a dependency analysis on the instructions to determine dependency...
6526514 Method and apparatus for power management interrupt processing in a computing system  
A method and apparatus for processing interrupts in a computing system include processing for ordering a plurality of interrupts for at least one processor. Such interrupts include system event...
6516403 System for synchronizing use of critical sections by multiple processors using the corresponding flag bits in the communication registers and access control register  
A hardware arrangement for implementing synchronization control between multiple processors is disclosed. The hardware arrangement is provided with a plurality of communication registers which are...
6516407 Information processor  
To an existing instruction set, newly added are a condition code conversion instruction for converting a first condition code (N, Z, OV, C) to a second condition code (V, S) based on a reference...
6504495 Clipping data values in a data processing system  
A clipping and quantization technique is described for producing clipped numbers in a range of 0 to Nāˆ’1 (from unclipped numbers in a range of āˆ’0.5N to (1.5Nāˆ’1)), where N is 2 m and m is the...
6502143 Intelligent interface cable assembly and method of providing the same  
A method and apparatus for interfacing a weighing scale and one or more peripheral devices which includes a single intelligent interface cable assembly connected between a weighing scale and a...
6499098 Processor with instruction qualifiers to control MMU operation  
A processor ( 100 ) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and...
6490647 Flushing stale data from a PCI bus system read prefetch buffer  
A system and method for flushing stale data from a read prefetch buffer of a PCI bus system which transfers data in the form of data streams of contiguous blocks. The PCI bus system comprises a...
6480913 Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter  
A system converts an input data stream in a first format (identified by a first stream code having at least two bits) into an output data stream in a second format. The system includes, among other...
6457118 Method and system for selecting and using source operands in computer system instructions  
According to the present invention, techniques for setting selected operand fields in pipelined architectures are provided. Methods and systems for efficiently selecting operand fields according to...
6449712 Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions  
A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating...
6446196 Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications  
A method, apparatus and computer program product are provided including one-of and one-of-and-jump instructions for use with processing data communications in a communications system. A one-of...
6427205 Digital signal processor and processor reducing the number of instructions upon processing condition execution instructions  
In a digital signal processor for pipeline processing divided into at least three steps, i.e., instruction fetch cycle, instruction decode cycle and instruction execution cycle, a value of a...
6412063 Multiple-operand instruction in a two operand pipeline and processor employing the same  
For use in a processor having a pipeline of insufficient width to convey all operands of a given multiple-operand instruction concurrently, a system for, and method of, processing the...
6405305 Rapid execution of floating point load control word instructions  
A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating...
6367004 Method and apparatus for predicting a predicate based on historical information and the least significant bits of operands to be compared  
In one method, a predicted predicate value may be determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one...
6360316 Method for fast detection of mutually exclusive predicated instructions  
A method for detecting independent predicated instructions comprises associating all instructions within a block of code with true and false bit vectors that have bit locations corresponding to...
6351806 Risc processor using register codes for expanded instruction set  
A RISC processor using a fixed length standard instruction word (32-bit) consisting of a fixed-length (6-bit) operation code and two register fields, uses one of the register fields to give certain...
6349383 System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution  
An apparatus and method are provided for combining multiple instructions prescribing accesses to a microprocessor stack into a single micro instruction. The apparatus includes a translator and...
6347392 Method for the control of an electronic circuit and control unit for its implementation  
A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control...
6339752 Processor emulation instruction counter virtual memory address translation  
When emulating a Target architecture on a Host system having a different architecture, virtual-to-real address translation is typically expensive in terms of computer cycles. The cost for...
6308256 Secure execution of program instructions provided by network interactions with processor  
A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the...
6308258 Data processing circuit with target instruction and prefix instruction  
A certain target instruction and a prefix instruction for expanding the function of that target instruction are input to the present data processing circuit. The data processing circuit analyses...
6298438 System and method for conditional moving an operand from a source register to destination register  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional...
6289439 Method, device and microprocessor for performing an XOR clear without executing an XOR instruction  
Improvements are made in how microprocessors execute logical exclusive OR instructions when the operands of this instruction are equal. XOR instructions with equal operands are used to clear...
6289440 Virtual computer of plural FPG's successively reconfigured in response to a succession of inputs  
A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each...
6282633 High data density RISC processor  
A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average...
6279096 Digital signal processing memory logic unit using PLA to modify address and data bus output values  
The inventive system and method provides a processing resource which performs bit reversing and Boolean algebraic operations. These operations are commonly needed by discrete transform algorithms...
6272622 Method of and circuit for instruction/data prefetching using non-referenced prefetch cache  
A method of and a circuit for instruction/data prefetching using a non-referenced prefetch cache, adapted to store instruction/data blocks prefetched in accordance with a variety of existing...
6253313 Parallel processor system for processing natural concurrencies and method therefor  
A computer processing system containing a plurality of identical processor elements each of which does not retain execution state information from prior operations. The plurality of identical...
6253314 Instruction set and executing method of the same by microcomputer  
A computer program product, method and apparatus for utilizing common prefix codes in computing instructions so as to reduce the number instructions required to perform identical operations for...
6237086 1 Method to prevent pipeline stalls in superscalar stack based computing systems  
An execution unit for a stack based computing system that can combine instructions into instruction groups for concurrent execution is provided. In accordance with one embodiment, the instructions...
6237085 Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation  
A processor includes execution resources and condition code logic. The execution resources execute an arithmetic or logical instruction by arithmetically or logically combining at least two...
6237087 Method and apparatus for speeding sequential access of a set-associative cache  
An embodiment of the invention is directed at a method for accessing a cache by detecting a branch instruction having an address and containing a first set of bits representing a displacement...
6233492 Process control system and method for transferring process data therefor  
A process control system includes a plurality of machine controllers for individually controlling a plurality of process chambers and a main controller for controlling the machine controllers. Each...
6233675 Facility to allow fast execution of and, or, and test instructions  
Improvements are made in how microprocessors execute AND, OR, and TEST instructions when the operands of this instruction are equal. AND/OR/TEST instructions with equal operands are used to set...
6219778 Apparatus for generating out-of-order results and out-of-order condition codes in a processor  
A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results...
Matches 151 - 200 out of 358 < 1 2 3 4 5 6 7 8 >