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9043583 Load/move and duplicate instructions for a processor  
A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent...
9043576 System and method for virtual machine conversion  
System and method for conversion of virtual machine files without requiring copying of the virtual machine payload (data) from one location to another location. By eliminating this step,...
9037813 Data accessing method for flash memory storage device having data perturbation module, and storage system and controller using the same  
A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation...
9037836 Shared load-store unit to monitor network activity and external memory transaction status for thread switching  
An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects...
9037838 Multiprocessor messaging system  
A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first...
9032174 Information processing apparatus for restricting access to memory area of first program from second program  
A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so...
9021237 Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread  
A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained...
9021233 Interleaving data accesses issued in response to vector access instructions  
A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by elements of earlier and a later vector instructions, one being a write instruction....
9015451 Processor including a cache and a scratch pad memory and memory control method thereof  
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data...
9015453 Packing odd bytes from two source registers of packed data  
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data...
9009452 Computing system with transactional memory using millicode assists  
A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a...
9009450 Mixed operand size instruction processing for execution of indirect addressing load instruction specifying registers for different size operands  
A data processing system 2 includes a processor core 4 and a memory 6. The processor core 4 includes processing circuitry 12, 14, 16, 18, 26 controlled by control signals generated by decoder...
9009444 System and method for LUN control management  
A method, computer program product, and computing system for receiving a reservation for a LUN from Host A, wherein the LUN is defined within a data array. A lock for the LUN is defined as Host A....
9003171 Page fault prediction for processing vector instructions  
A system including a processor that handles a TLB miss while executing a vector read instruction in a processor is described herein. During operation, the processor performs a lookup in a TLB for...
8984261 Store data forwarding with no memory model restrictions  
Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a...
8977815 Control of entry of program instructions to a fetch stage within a processing pipepline  
A processing pipeline 6, 8, 10, 12 is provided with a main query stage 20 and a fetch stage 22. A buffer 24 stores program instructions which have missed within a cache memory 14. Query generation...
8977816 Cache and disk management method, and a controller using the method  
A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid...
8977837 Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes  
At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second...
8972704 Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory  
A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by...
8972705 Executing instructions for managing constant pool base register used for accessing constants during subroutine execution  
A constant data accessing system having a constant pool comprises a computer processor having a constant pool base register, a compiler having a constant pool handler, and an instruction set...
8966231 Modifying commands  
The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes...
8966635 Software module object analysis  
In one implementation, an object analysis system identifies an object within a software module, and determines a size of the object based on at least one operation within the software module. The...
8959304 Management of data processing security in a secondary processor  
A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory...
8959339 Method and system for preventing unauthorized processor mode switches  
A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple...
8934332 Multi-threaded packet processing  
A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A...
8935514 Optimizing performance of instructions based on sequence detection or information associated with the instructions  
In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first...
8930682 Handling media streams in a programmable bit processor  
In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a...
8930962 Processing unexpected messages at a compute node of a parallel computer  
Methods, apparatuses, and computer program products for processing unexpected messages at a compute node of a parallel computer are provided. Embodiments include receiving, by the compute node, a...
8930638 Method and apparatus for supporting target-side security in a cache coherent system  
A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by...
8930664 Method and apparatus for transferring data from a first domain to a second domain  
Data is written from a first domain to a FIFO memory buffer in a second domain. The first domain uses a first clock signal, the second domain uses a second clock signal and the memory buffer uses...
8918625 Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison  
A processor that executes instructions out of program order is described. In some implementations, a processor detects whether a second memory operation is dependent on a first memory operation...
8918627 Multithreaded processor with multiple concurrent pipelines per thread  
A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of...
8914620 Method and system for reducing abort rates in speculative lock elision using contention management mechanisms  
Hardware-based transactional memory mechanisms, such as Speculative Lock Elision (SLE), may allow multiple threads to concurrently execute critical sections protected by the same lock as...
8904154 Execution migration  
An execution migration approach includes bringing the computation to the locus of the data: when a memory instruction requests an address not cached by the current core, the execution context...
8904153 Vector loads with multiple vector elements from a same cache line in a scattered load operation  
Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of...
8898439 Serial flash memory and address transmission method thereof  
A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second...
8892848 Processor and system using a mask register to track progress of gathering and prefetching elements from memory  
A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and...
8891757 Programmable cryptographic integrated circuit  
A cryptographic integrated circuit including a programmable main processor for executing cryptographic functions, an internal memory, and a data transmission bus to which the main processor and...
8893153 Inter-thread data communications in a computer processor  
A first set of one or more hardware threads for receiving messages sent from hardware threads are registered. After receiving indications of a message location value and a number, the message...
8880809 Memory controller with inter-core interference detection  
Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus...
8880850 Low power, high performance, heterogeneous, scalable processor architecture  
One embodiment of the present includes a heterogeneous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer...
8860558 Remote control device and communication system  
A remote control device includes: a vibration power generator configured to convert externally applied vibrations to electric power; a storage section charged with the electric power obtained by...
8850167 Loading/discarding acquired data for vector load instruction upon determination of prediction success of multiple preceding branch instructions  
Provided is a processor including an instruction issue unit that issues a vector load instruction read from a main memory based on branch target prediction of a branch target in a branch...
8850166 Load pair disjoint facility and instruction therefore  
A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands...
8843731 Memory device using extended interface commands  
A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the...
8838906 Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution  
In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory,...
8838944 Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitives  
Implementation primitives for concurrent array-based stacks, queues, double-ended queues (deques) and wrapped deques are provided. In one aspect, each element of the stack, queue, deque or wrapped...
8832325 Transfer between storage devices  
Migrating data from a source storage device to a target storage device includes creating new paths to the target storage device, setting the target storage device to a state where I/O operations...
8832413 Processing system with interspersed processors and communication elements having improved wormhole routing  
A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through...
8812824 Method and apparatus for employing multi-bit register file cells and SMT thread groups  
There are provided methods and apparatus for multi-bit cell and SMT thread groups. An apparatus for a register file includes a plurality of multi-bit storage cells for storing a plurality of bits...