Matches 1 - 50 out of 565 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
7627744 External memory accessing DMA request scheduling in IC of parallel processing engines according to completion notification queue occupancy level  
An integrated circuit comprises an external memory, a plurality of parallel connected Vector Processing Engines (VPEs), and an External Memory Unit (EMU) providing a data transfer path between the...
7627743 Method and circuit implementation for multiple-word transfer into/from memory subsystems  
A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a...
7627698 Methods and apparatus for providing data transfer control  
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing...
7624251 Instructions for efficiently accessing unaligned partial vectors  
One embodiment of the present invention provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch...
7620797 Instructions for efficiently accessing unaligned vectors  
One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is...
7617386 Scheduling thread upon ready signal set when port transfers data on trigger time activation  
A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the...
7613909 Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor  
A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute...
7606998 Store instruction ordering for multi-core processor  
A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by...
7606974 Automatic caching generation in network applications  
Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads...
7594250 Method and system of program transmission optimization using a redundant transmission sequence  
A system and method of optimizing transmission of a program to multiple users over a distribution system, with particular application to video-on-demand for a CATV network. The system includes, at...
7594101 Secure digital processing unit and method for protecting programs  
A digital processing unit for executing program instructions stored in at least two memories and including at least one first register of temporary storage of the operator of a current instruction...
7594100 Efficient store queue architecture  
One embodiment of the present invention provides a store queue that applies the stores to a memory subsystem in program order. This store queue includes a content-addressable memory (CAM), which...
7594060 Data buffer allocation in a non-blocking data services platform using input/output switching fabric  
Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement...
7587577 Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content  
A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing...
7583663 Systems and methods for converting a P packet/cycle datapath to a Q packet/cycle datapath  
A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue during...
7577105 Cooperation information managing apparatus and gateway apparatus for use in cooperation information managing system  
In a system including a first unit retaining a first identifier and a second unit retaining a second identifier for reading out the first identifier from the first unit to transmit, as cooperation...
7568087 Partial load/store forward prediction  
In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load...
7565510 Microprocessor with a register selectively storing unaligned load instructions and control method thereof  
A load/store unit includes a Top register for storing a value retained before loading to a load destination register and a saved register capable of storing data retained to the Top register. When...
7555637 Multi-port read/write operations based on register bits set for indicating select ports and transfer directions  
A computer ( 12 ) having multiple data paths ( 38 a - d ) connecting to other devices, which may be similar computers. A register ( 40 d ) is provided that has bits ( 110 ) programmatically...
7552247 Increased computer peripheral throughput by using data available withholding  
A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and...
7546441 Coprocessor interface controller  
A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the...
7543287 Using a block device interface to invoke device controller functionality  
In one embodiment, a standard block device command is received at a device controller. The standard block device command is addressed to a virtual block device associated with the device...
7539844 Prefetching indirect array accesses  
A method for prefetching data from an array, A, the method including: detecting a stride, dB, of a stream of index addresses of an indirect array, B, contents of each index address having...
7533238 Method for limiting the size of a local storage of a processor  
A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a...
7525457 Transforming design objects in a computer by converting data sets between data set types  
A computer implemented method converts a data set of a first type to a data set type of a second type. The method includes casting up a first data set of a first type to a prescribed data set type...
7523449 System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture  
A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable...
7523230 Device and method for maximizing performance on a memory interface with a variable number of channels  
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
7519797 Hierarchical multi-precision pipeline counters  
An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is...
7519796 Efficient utilization of a store buffer using counters  
An apparatus and method for efficiently managing store buffer operations is described in connection with a multithreaded multiprocessor chip. A CMT processor keeps track of stores by maintaining...
7516310 Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor  
A method for reducing the number of times in-flight loads must be searched by store instructions in a multi-threaded processor. A load issue for a thread t_old is frozen for a number of cycles. A t...
7516309 Method and apparatus for conditional memory ordering  
A method and apparatus for conditional memory ordering are disclosed. The cost of memory ordering is reduced by determining circumstances in which a memory ordering operation is unnecessary and...
7516306 Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies  
The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend...
7509484 Handling cache misses by selectively flushing the pipeline  
An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT processor keeps track of load misses...
7502917 High speed memory cloning facility via a lockless multiprocessor mechanism  
A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an...
7500049 Providing a backing store in user-level memory  
In one embodiment, the present invention includes a method for requesting an allocation of memory to be a backing store for architectural state information of a processor and storing the...
7496737 High priority guard transfer for execution control of dependent guarded instructions  
A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of...
7496721 Packet processor memory interface with late order binding  
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between the...
7496673 SIMD-RISC microprocessor architecture  
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and...
7493481 Direct hardware processing of internal data structure fields  
In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code...
7493447 System and method for caching sequential programs  
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
7490178 Threshold on unblocking a processing node that is blocked due data packet passing  
A threshold mechanism is provided so that a producer and a corresponding consumer, executing on the same resource (e.g., CPU) are able to switch context between them in a manner that reduces the...
7487304 Packet processor memory interface with active packet list  
A mechanism receives start and done commands containing packet identifiers or sequence numbers from a packet processing engine for packets for which processing is being started and for which...
7484080 Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer  
One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order....
7484017 Dequeuing from a host adapter two-dimensional queue  
A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is...
7480788 Command time-out managing apparatus  
The present information processing apparatus, which receives and executes commands, monitors time-outs of commands with reliability, thereby making it possible to prevent a command initiator from...
7480771 Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged  
We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated,...
7480754 Assignment of queue execution modes using tag values  
The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host....
7478209 Packet processor memory interface with conflict detection and checkpoint repair  
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
7475201 Packet processor memory interface with conditional delayed restart  
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
7475200 Packet processor memory interface with write dependency list  
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
Matches 1 - 50 out of 565 1 2 3 4 5 6 7 8 9 10 11 12 >