Matches 201 - 250 out of 568 < 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
6965985 Sign generation bypass path to aligner for reducing signed data load latency  
A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part...
6963967 System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture  
Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In...
6963934 Hibernation of computer systems  
An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed,...
6961861 Globally clocked interfaces having reduced data path length  
A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data...
6957324 Computer system and method of controlling computation  
A vector computer system includes a plurality of memory banks 40 , a vector processor 11 , and a plurality of additional processing units 30 each of which is connected to one of the memory...
6941390 DMA device configured to configure DMA resources as multiple virtual DMA channels for use by I/O resources  
Various embodiments of a system and method for configuring a set of DMA resources as multiple virtual DMA channels are disclosed. In one embodiment, a system may include a context memory configured...
6938105 Data apparatus and method having DMA circuitry to efficiently transfer multivalued bit-plane data  
A data processing apparatus improves speed and efficiency of transfer of bit data, especially, multivalue data bit plane. For this purpose, a memory 50 holds four 8-bit multivalue data per 1...
6931515 Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loads  
A method and system for determining, at run-time, whether or not to defer an exception that arises during execution of a control-speculative load instruction based on a recent history of execution...
6928534 Forwarding load data to younger instructions in annex  
A method and computer system for bypassing load data to younger instructions are provided. The method and computer system contemplate a microprocessor that manages interlock conditions for load...
6928535 Data input/output configuration for transfer among processing elements of different processors  
An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting...
6925535 Program control flow conditioned on presence of requested data in cache memory  
Method and apparatus for conditioning program control flow on the presence of requested data in a cache memory. In a data processing system that includes a cache memory and a system memory coupled...
6918030 Microprocessor for executing speculative load instructions with retry of speculative load instruction without calling any recovery procedures  
A system, method and apparatus is provided that splits a microprocessor load instruction into two (2) parts, a speculative load instruction and a check speculative load instruction. The speculative...
6915415 Method and apparatus for mapping software prefetch instructions to hardware prefetch logic  
A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking...
6912596 Automatic resume from suspend for IEEE-1394 PHY  
A system and process are disclosed for automatically resuming data communication using an IEEE-1394 PHY when communication is suspended because input bias is momentarily lost. The PHY determines...
6901505 Instruction causing swap of base address from segment register with address from another register  
A processor is described which executes an instruction defined to swap the contents of at least one special purpose register (e.g. an MSR or a segment register) and another register. In some...
6898697 Efficient method for mode change detection and synchronization  
A processor is configured to operate in a modes which utilize segmentation and which do not utilize segmentation. The processor includes circuitry which is configured to detect and respond to mode...
6883086 Repair of mis-predicted load values  
When fetching a load value for a load instruction results in a cache miss, the load instruction and any load-dependent instructions may be speculatively executed with a predicted load value and...
6883087 Processing of binary data for compression  
Binary data is processed and organized by determining patterns specific for the binary data in a software package. Code sections may be split from an instruction according to the code section type...
6883037 Fast data decoder that operates with reduced output buffer bounds checking  
Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings...
6880071 Selective signalling of later reserve location memory fault in compound compare and swap  
A sequentially performed implementation of a compound compare-and-swap (nCAS) operation has been developed. In one implementation, a double compare-and-swap (DCAS) operation does not result in a...
6868491 Processor and method of executing load instructions out-of-order having reduced hazard penalty  
A processor having a reduced data hazard penalty includes a register set, at least one execution unit that executes load instructions to transfer data into the register set, and a load queue. The...
6862679 Synchronization of load operations using load fence instruction in pre-serialization/post-serialization mode  
A method and apparatus for synchronizing load operations. In one embodiment, an apparatus includes a decode circuit to decode a load fence instruction. An execution unit executes the load fence...
6862677 System and method for eliminating write back to register using dead field indicator  
An instruction execution device and method are disclosed for reducing register write traffic within a processor. The instruction execution device includes an instruction pipeline for producing a...
6857032 Image data input device  
An image data input device comprises a scanner, which has a SCSI driver and a connector, and a personal computer, which has a SCSI cable. The scanner is connected to the personal computer through...
6854049 Method of handling instructions within a processor with decoupled architecture, in particular a processor for digital signal processing, and corresponding processor  
A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is...
6854048 Speculative execution control with programmable indicator and deactivation of multiaccess recovery mechanism  
Mechanisms and techniques operate in a computerized device to enable or disable speculative execution of instructions such as load instructions on one or more processors in the computerized device....
6851044 System and method for eliminating write backs with buffer for exception processing  
An instruction execution device and method are disclosed for reducing register write traffic within a processor with exception routines. The instruction execution device includes an instruction...
6845442 System and method of using speculative operand sources in order to speculatively bypass load-store operations  
A system may include a scheduler and an execution core. The scheduler includes an entry allocated to an operation. The entry includes a non-speculative tag and a speculative tag, and both the...
6842851 Reading a selected register in a series of computational units forming a processing pipeline upon expiration of a time delay  
A system and method for reading register contents from a computational pipeline having a plurality of computational units. The system includes a readback bus and a read control unit. The readback...
6836839 Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements  
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of...
6832308 Apparatus and method for instruction fetch unit  
An apparatus is described comprising a signal indicative of which of a plurality of data structures stored in a queue desire to issue from the queue. The apparatus also has a content addressable...
6829700 Circuit and method for supporting misaligned accesses in the presence of speculative load instructions  
There is disclosed a data processor comprising: 1) an instruction execution pipeline comprising N processing stages for executing a load instruction; 2) a status register for storing a modifiable...
6829696 Data processing system with register store/load utilizing data packing/unpacking  
A data processing system (e.g., microprocessor 30 ) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor...
6826636 Method and architecture capable of programming and controlling access data and instructions  
A method and an architecture capable of programming and controlling access of data and instructions are provided. There are provided a plurality of data transfer levels, in which a current data...
6826679 Processor with pointer tracking to eliminate redundant memory fetches  
A processor is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction...
6823403 DMA mechanism for high-speed packet bus  
A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests...
6820195 Aligning load/store data with big/little endian determined rotation distance control  
Embodiments of the present invention are directed to an architecture structured to handle unaligned memory references. In one embodiment, a method for loading unaligned data stored in a plurality...
6820191 Apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor  
An apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor is provided. The method includes...
6816960 Cache consistent control of subsequent overlapping memory access during specified vector scatter instruction execution  
A vector artchitecture processing unit according to the present invention comprises a vector scatter (VSC) address coincidence detection unit 3 that comprises registers in which an area start...
6813706 Data processing system and multiprocessor system  
The present invention provides an information processing system that can have the optimum number of FIFO stages dynamically at any given time so that the system makes it possible to omit analyzing...
6801996 Instruction code conversion unit and information processing system and instruction code generation method  
An instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes...
6801961 Method for solving intermission of streaming data and associated device thereof  
A method for solving intermission of streaming data. A digital controller is used to transmit streaming data stored in a storage unit. The digital controller includes a base recording unit and a...
6799267 Packet processor  
A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the...
6799265 Dependency checking for reconfigurable logic  
A data dependency checking table is used with a reconfigurable chip. A control processing chip on the reconfigurable chip can load variable size blocks of data to and from reconfigurable slices on...
6795911 Computing device having instructions which access either a permanently fixed default memory bank or a memory bank specified by an immediately preceding bank selection instruction  
A computing device accesses multiple memory banks, which are selected by a bank selection instruction. The memory bank selected by the bank selection instruction is accessed by a memory access...
6792485 Data output control apparatus connected via a network to a portable terminal and a plurality of printing apparatuses  
The invention provides a data output control apparatus which is suitable for allowing detailed information on a network to be readily obtained. A data output control terminal selects one of...
6782435 Device for spatially and temporally reordering for data between a processor, memory and peripherals  
A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from...
6782470 Operand queues for streaming data: A processor register file extension  
The register file of a processor includes embedded operand queues. The configuration of the register file into registers and operand queues is defined dynamically by a computer program. The...
6779052 Electronic apparatus, system and method for controlling communication among devices coupled through different interfaces  
An electronic apparatus, system and method are provided for controlling different types of electronic devices coupled through a serial bus. The electronic apparatus may include an Integrated Drive...
6775740 Processor having a selector circuit for selecting an output signal from a hit/miss judgement circuit and data from a register file  
A processor for carrying out an arithmetic operation in accordance with a program using data stored in a memory connected to the outside includes: a register file having at least one register for...
Matches 201 - 250 out of 568 < 1 2 3 4 5 6 7 8 9 10 11 12 >