Matches 151 - 200 out of 568 < 1 2 3 4 5 6 7 8 9 10 11 12 >
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7162616 Floating point unit pipeline synchronized with processor pipeline  
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions...
7155721 Method and apparatus for communicating information between lock stepped processors  
An apparatus for communicating between lock step is incorporated on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence,...
7143265 Computer program product memory access system  
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred...
7136990 Fast POP operation from RAM cache using cache row value stack  
A method and apparatus for performing a fast pop operation from a random access cache is disclosed. The apparatus includes a stack onto which is pushed the row and way of push instruction data...
7136979 Copy engine and a method for data movement  
A copy engine ( 104 ) is provided as an interface between firmware ( 108 ) and memory space ( 106 ) for carrying out copy operations. The copy engine has a first register ( 202, 203 ) to point to a...
7134001 Pipeline replay support for unaligned memory operations  
Instructions asserted in a microprocessors instruction pipeline ( 3 ) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline ( 5 ) that...
7133040 System and method for performing an insert-extract instruction  
An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is...
7130934 Methods and apparatus for providing data transfer control  
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing...
7127590 Reconfigurable VLIW processor  
Disclosed is a computer processor ( 300 ) comprising a plurality of processing units (FU_n) and communication means ( 302 ) by which the plurality of processing units are interconnected. The...
7120783 System and method for reading and writing a thread state in a multithreaded central processing unit  
A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous...
7120779 Address offset generation within a data processing system  
A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction...
7114086 System for reduced power consumption by monitoring instruction buffer and method thereof  
A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated with an instruction buffer is monitored to determine whether power...
7111155 Digital signal processor computation core with input operand selection from operand bus for dual operations  
A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a...
7107402 Packet processor memory interface  
A mechanism processes memory reads and writes in a packet processor. Each memory access has an associated sequence number and information is maintained allowing the detection of memory conflicts....
7107436 Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect  
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of...
7107432 VLIW processor with data spilling means  
A VLIW processor comprising: a plurality of functional units ( 1, 3 ); a distributed register file ( 4 ) comprising a plurality of segments ( 5, 7, 9 ), the distributed register file ( 4 ) being...
7096280 Data output controller  
An objective of the present invention is to provide a data output controller ideally suited for easily obtaining detailed information available on a network. A data output control terminal 300 ...
7096346 Microprocessor having instructions for exchanging values between two registers or two memory locations  
A microprocessor includes internal registers, an arithmetic and logic unit, and reads a program memory and executes an instruction set stored therein. The instruction set includes at least one...
7093102 Code sequence for vector gather and scatter  
Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required...
7089364 System and method to stall dispatch of gathered store operations in a store queue using a timer  
A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations...
7089408 Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution  
A system and method to re-fetch operand data lost for instructions with operands greater than eight bytes in length due to line invalidation due to storage update from a single or plurality of...
7089407 Packet processing device processing input packet data in a packet routing device  
A packet processing device which can reserve a calculation time for each instruction procedure execution unit independent of the data length of a packet by sequentially selecting an instruction...
7085913 Hub/router for communication between cores using cartesian coordinates  
A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global...
7080236 Updating stack pointer based on instruction bit indicator without executing an update microinstruction  
A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also...
7076636 Data storage system having an improved memory circuit board configured to run scripts  
A data storage system includes a set of storage devices, a memory circuit board that includes a cache to temporarily store copies of data elements stored in the set of storage devices, and a...
7062767 Method for coordinating information flow between components  
A method of efficiently coordinating the communication of data and commands between multiple entities in a system is disclosed. A transaction protocol enabling centralized scheduling of chains of...
7062638 Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores  
An electronic device including a predictor that has a collision history table (CHT) is presented. An extended load buffer is connected to the predictor. Also included is a marking unit, a comparing...
7058794 Apparatus and method for masked move to and from flags register in a processor  
A method and apparatus are provided for storing a flags register in a processor. In response to a macro instruction directing the store operation, such as a push flags macro instruction, a mask is...
7058049 Load store queue applied to processor  
An in-order state queue holds store tags as in-order information about store instructions. A temporal store cache, which uses store addresses as indexes, holds store tags and store values. A first...
7058735 Method and apparatus for local and distributed data memory access (“DMA”) control  
An apparatus for local direct memory access control includes a processor unit for generating a direct memory access designator when needed data is not available and continuing processing which does...
7051194 Self-synchronous transfer control circuit and data driven information processing device using the same  
When an instruction decoder decodes an instruction code included in packet data, a copy flag and copy number information are provided to a self-synchronous transfer control circuit. In the...
7051191 Resource management using multiply pendent registers  
A resource management system and method is disclosed. The resource management system and method enable first and second instructions, each of which requires access to a memory resource, to be...
7047393 Coprocessor processing instruction with coprocessor ID to broadcast main processor register data element to coprocessor multi-element register  
A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the...
7043627 SIMD operation system capable of designating plural registers via one register designating field  
In view of a necessity of alleviating factors obstructing an effect of SIMD operation such as in-register data alignment in high speed formation of an SIMD processor, numerous data can be supplied...
7039918 Service processor and system and method using a service processor  
A service processor is provided for a computer system that includes a host processor and the service processor. The service processor includes a management interface including a first port forming...
7032102 Signal processing device and method for supplying a signal processing result to a plurality of registers  
A signal processing device and method of supplying a signal processing result to a plurality of registers arranged in different register files. A plurality of different register files are selected...
7028166 System and method for linking speculative results of load operations to register values  
A system may include a memory file, which includes an entry configured to store a first addressing pattern and a first tag, and an execution core coupled to the memory file. The memory file may be...
7024537 Data speculation based on addressing patterns identifying dual-purpose register  
A system may include a memory file and an execution core. The memory file may include an entry configured to store an addressing pattern and a tag. If an addressing pattern of a memory operation...
7016984 System controller using plural CPU's  
In a system controller in which a plurality of CPUs connected through a shared bus are connected to a plurality of memory units or IO devices through a bus for separate transfer of a read...
7016983 System and method for controlling a communication bus  
A method for controlling communication. The method sends a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus, sends a...
7000090 Center focused single instruction multiple data (SIMD) array system  
A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of...
7000092 Heterogeneous multi-processor reference design  
The present invention is directed to a system and method for heterogeneous multiprocessor reference design. In an aspect of the present invention, a method of designing a multiprocessor integrated...
6988188 Data object architecture and method for xDSL ASIC processor  
A structure for a data object is disclosed with a field and format structure optimized for use by a set of pipeline stages that are interconnected logically through a common pipeline memory. The...
6983360 Program loading mechanism through a single input data path  
Pieces of input data, which can be either setup data or program data with an associated identifier, are provided to a processing engine through a single input data path. After a system initially...
6981110 Hardware enforced virtual sequentiality  
A mechanism processes memory reads and writes in a packet processor. Each memory access has an associated sequence number and information is maintained allowing the detection of memory conflicts....
6978360 Scalable processor  
A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation...
6976155 Method and apparatus for communicating between processing entities in a multi-processor  
A method and apparatus for synchronizing and communicating between processing entities, such as cores or threads, in a multiprocessor. Two registers are used as a “hardware mailbox” by two...
6970997 PROCESSOR, MULTIPROCESSOR SYSTEM AND METHOD FOR SPECULATIVELY EXECUTING MEMORY OPERATIONS USING MEMORY TARGET ADDRESSES OF THE MEMORY OPERATIONS TO INDEX INTO A SPECULATIVE EXECUTION RESULT HISTORY STORAGE MEANS TO PREDICT THE OUTCOME OF THE MEMORY OPERATION  
When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning...
6970996 Operand queue for use in a floating point unit to reduce read-after-write latency and method of operation  
A floating point unit includes floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that...
6967950 Pull transfers and transfer receipt confirmation in a datapipe routing bridge  
In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal...
Matches 151 - 200 out of 568 < 1 2 3 4 5 6 7 8 9 10 11 12 >