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7315932 Data processing system having instruction specifiers for SIMD register operands and method thereof  
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of...
7308560 Processing unit  
A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for...
7305500 Sram controller for parallel processor architecture including a read queue and an order queue for handling requests  
A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes...
7302380 Simulation apparatus, method and program  
A simulation apparatus for simulating a pipeline processor including a pipeline simulation unit and an instruction simulation unit. The simulation apparatus includes a pipeline simulation unit is...
7290289 Processor with several calculating units  
A processor comprises a first calculating unit, a second calculating unit and a control means for controlling the two calculating units, such that they selectively operate in a high security mode...
7287151 Communication path to each part of distributed register file from functional units in addition to partial communication network  
A VLIW processor comprising a plurality of functional units ( 1, 3, 5, 7 ), a distributed register file ( 9, 11, 13, 15 ) accessible by the functional units ( 1, 3, 5, 7 ), a partially connected...
7284118 Method and apparatus for synchronizing load operations  
A method and apparatus for synchronizing load operations. In one embodiment, an apparatus includes a decode circuit to decode a load fence instruction. An execution unit executes the load fence...
7280539 Data driven type information processing apparatus  
In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other...
7275148 Data processing system using multiple addressing modes for SIMD operations and method thereof  
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of...
7272703 Program controlled embedded-DRAM-DSP architecture and methods  
An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register files, set of functional units, and...
7263601 Sequencer unit with instruction buffering  
A sequencer unit includes a first instruction processing unit, an instruction buffer and a second instruction processing unit. The first instruction processing unit is adapted for receiving and...
7260709 Processing method and apparatus for implementing systolic arrays  
The present invention relates to a processing method and apparatus for implementing a systolic-array-like structure. Input data are stored in a depth-configurable register means (DCF) in a...
7260710 Initializing function block registers using value supplying setting interface coupled to table linking block identifier to multiple register address set  
A processor ( 1 ) having an instruction memory ( 2 ) supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit ( 3 ), and address values...
7257814 Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors  
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism...
7254699 Aligning load/store data using rotate, mask, zero/sign-extend and or operation  
The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is...
7254696 Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests  
A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC...
7249245 Globally observing load operations prior to fence instruction and post-serialization modes  
A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache...
7249244 Data processing system  
The invention relates to a processing system comprising a calculation device comprising at least one calculation unit ( 13 ), a storage device and a system for switching between the storage device...
7243215 System and method for utilizing a scoreboard to indicate information pertaining to pending register writes  
Generally, the present invention provides a system and method for processing instructions of a computer program and for indicating instruction attribute and/or status information so that the...
7243218 Method and processing unit for selective value prediction using data cache hit/miss information and/or dependency depth information  
The present invention relates to a processing unit for executing instructions in a computer system and to a method in such a processing unit. According to the present invention a decision is made...
7243216 Apparatus and method for updating a status register in an out of order execution pipeline based on most recently issued instruction information  
An apparatus and method is disclosed for updating a status register in an out of order execution pipeline. In one embodiment a dispatch unit in a floating point unit sets a MRI bit flag that...
7240175 Scheduling data frames for processing: apparatus, system and method  
A scheduler in, for example, an off-load engine reports events for processing data frames to processing engines. Each event to report has associated to it an event information to report to a...
7240183 System and method for detecting instruction dependencies in multiple phases  
Systems and methods for determining dependencies between processor instructions in multiple phases. In one embodiment, a partial comparison is made between the addresses of a sequence of...
7234005 System and method of setting parameters of peripheral device when an operation ratio of a command exceeds predetermined value  
A method of setting a parameter of a peripheral device, for controlling an operation of the peripheral device includes collecting and storing a command issued for the peripheral device by an...
7228401 Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor  
The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to...
7222226 System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation  
A system may include a dispatch unit, a scheduler, and an execution core. The dispatch unit may be configured to modify a load operation to include a register-to-register move operation in response...
7219212 Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion  
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one...
7219215 Data processing apparatus and method for moving data elements between specified registers and a continuous block of memory  
A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers...
7219322 Multiple propagation speeds of signals in layered circuit apparatus  
A first signal passes through a first layer of a circuit apparatus at a first propagation speed, and a second signal passes through a second layer of the circuit apparatus at a second propagation...
7216205 Cache line ownership transfer in multi-processor computer systems  
Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory...
7210026 Virtual register set expanding processor internal storage  
A processor includes a set of registers, each individually addressable using a corresponding register identification, and plural virtual registers, each individually addressable using a...
7206925 Backing Register File for processors  
A processor is defined by a new architectural feature called a Backing Register File, where a Backing Register File is a set of randomly accessible registers capable of holding values, and further...
7206857 Method and apparatus for a network processor having an architecture that supports burst writes and/or reads  
A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth...
7203809 Data transfer control method, and peripheral circuit, data processor and processing system for the method  
A memory 1 performs its internal operation in response to access requests ( 200, 201 and 202 ) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 ...
7200138 Physical medium dependent sub-system with shared resources for multiport xDSL system  
A physical medium dependent (PMD) transport subsystem is disclosed which is used in an xDSL communication system. The PMD subsystem coordinates movement of data from an analog front end to a...
7197625 Alignment and ordering of vector elements for single instruction multiple data processing  
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a...
7191318 Native copy instruction for file-access processor with copy-rule-based validation  
A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch....
7188233 System and method for performing floating point store folding  
A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a...
7188234 Run-ahead program execution with value prediction  
A data processing apparatus, a computer, an article including a machine-accessible medium, and a method of processing data are disclosed. The data processing apparatus may include a pair of...
7185125 Device for transferring data via write or read pointers between two asynchronous subsystems having a buffer memory and plurality of shadow registers  
Device for transferring data between two asynchronous systems communicating via a FIFO memory. The first system comprises a write pointer register and the second system comprises a read pointer...
7185184 Processor system, especially a processor system for communications devices  
The invention relates to a processor system which is configured as a communications controller and which comprises a central processor unit ( 1 ) for executing instructions filed in a program...
7181562 Wired endian method and apparatus for performing the same  
A method and associated apparatus is provided for operating an electronic device in accordance with a wired endian format. More specifically, the wired endian format requires multi-byte values be...
7181598 Prediction of load-store dependencies in a processing agent  
In a processing core, a newly received load instruction may be dependent upon a previously received store instruction. The core may include a predictor to predict such dependencies and provide an...
7178010 Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack  
An internal call/return stack (CRS) correction apparatus in a pipelined microprocessor is disclosed. Each time the microprocessor updates the CRS in response to a call or return instruction...
7178009 Different register data indicators for each of a plurality of central processing units  
A digital signal processor may include a plurality of processing elements that are coupled together to accomplish a specialized function. Each processing element may utilize the same shared storage...
7174428 Method and system for transforming memory location references in instructions  
Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted...
7174394 Multi processor enqueue packet circuit  
The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager...
7165167 Load store unit with replay mechanism  
A microprocessor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to...
7165128 Multifunctional I/O organizer unit for multiprocessor multimedia chips  
An apparatus and method for providing enhanced performance for multi-processor multimedia chips. In one embodiment, the present invention is comprised of a data and communication apparatus coupled...
7162615 Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch  
Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to...
Matches 101 - 150 out of 568 < 1 2 3 4 5 6 7 8 9 10 11 12 >