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7478209 |
Packet processor memory interface with conflict detection and checkpoint repair
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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7475200 |
Packet processor memory interface with write dependency list
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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7475201 |
Packet processor memory interface with conditional delayed restart
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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7472260 |
Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion
In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store...
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7472390 |
Method and apparatus to enable execution of a thread in a multi-threaded computer system
Briefly, in accordance with an embodiment of the invention, an apparatus and method to enable execution of a thread in a multi-threaded computer system is provided. The method may include enabling...
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7464251 |
Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements
A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data...
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7463640 |
Self-synchronous FIFO memory device
A self-synchronous FIFO memory device ( 100 ) has a structure in which n self-synchronous data transmission lines ( 111 - 11 n ) are arrayed in parallel. An input control section ( 101 ) selects...
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7458078 |
Apparatus and method for autonomic hardware assisted thread stack tracking
Method and apparatus for tracking thread stacks during a trace of a computer program. Hardware assistance mechanisms allow a processor to autonomically maintain a thread work area for each thread...
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7447871 |
Data access program instruction encoding
A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit...
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7447877 |
Method and apparatus for converting memory instructions to prefetch operations during a thread switch window
A method and apparatus for converting memory instructions to prefetch operations during a thread switch window is disclosed. In one embodiment, memory access instructions that are already inside an...
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7447856 |
Copy engine and a method for data movement
A copy engine ( 104 ) is provided as an interface between firmware ( 108 ) and memory space ( 106 ) for carrying out copy operations. The copy engine has a first register ( 202, 203 ) to point to a...
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7444498 |
Load lookahead prefetch for microprocessors
The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the...
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7441107 |
Utilizing an advanced load address table for memory disambiguation in an out of order processor
Embodiments include a system for minimizing storage space required for tracking load instructions through a pipeline in a processor. Store instructions are tracked in a separate queue and only load...
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7441102 |
Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory
An integrated circuit comprises a processor configured for fetching and executing opcodes, a system bus, and a memory coupled to the processor via the system bus. The memory includes logic...
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7437521 |
Multistream processing memory-and barrier-synchronization method and apparatus
A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that...
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7437724 |
Registers for data transfers
A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a...
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7428618 |
Apparatus and method for interfacing with a high speed bi-directional network
A method and apparatus for processing a bi-directional dataflow are disclosed which permits the transparent movement of data from one processor to another via a shared memory fabric which is...
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7426629 |
Processing activity masking in a data processing system
A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the...
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7418583 |
Data dependency detection using history table of entry number hashed from memory address
A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least...
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7415597 |
Processor with dependence mechanism to predict whether a load is dependent on older store
A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store...
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7415594 |
Processing system with interspersed stall propagating processors and communication elements
A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one...
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7412587 |
Parallel operation processor utilizing SIMD data transfers
A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit...
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7406588 |
Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer
A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid...
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7401209 |
Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction
A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load...
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7398376 |
Instructions for ordering execution in pipelined processes
Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory...
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7395410 |
Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor
A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an...
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7395538 |
Scalable packet processing systems and methods
A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data...
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7395358 |
Intelligent storage engine for disk drive operations with reduced local bus traffic
For attached disk drive operations such a file copy and move, as well as more elaborate processes such as searching, virus-scanning and volume merge, a novel intelligent storage engine concept is...
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7392369 |
Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check
Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine...
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7386706 |
System and software for matched aligned and unaligned storage instructions
A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group...
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7383425 |
Massively reduced instruction set processor
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to...
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7380106 |
Method and system for transferring data between a register in a processor and a point-to-point communication link
A method and a system for transferring data between a register in a processor and a point-to-point communications link. More specifically, blocking and non-blocking methods are described to get and...
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7380107 |
Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss
Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor...
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7380100 |
Data processing system and control method utilizing a plurality of date transfer means
The present invention provides a data processing system that includes a plurality of processing units and first, second, and third data transfer means. The first data transfer means connects a...
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7373481 |
Distributed-structure-based parallel module structure and parallel processing method
A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1...
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7370123 |
Information processing apparatus
A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address...
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7370181 |
Single stepping a virtual machine guest using a reorder buffer
Embodiments of apparatuses, systems, and methods for single stepping a virtual machine guest using a reorder buffer are disclosed. In one embodiment, an apparatus includes a sequencer and a reorder...
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RE40306 |
End-of-scan reporting system
A reporting system capable of reporting the end of a scanning session to a user through existing computer peripheral devices is proposed. By reporting at the end of a scanning session, the user can...
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7363472 |
Memory access consolidation for SIMD processing elements having access indicators
A data processing apparatus includes a SIMD (Single Instruction Multiple Data) array ( 10 ) of processing elements. The processing elements are operably divided into a plurality of processing...
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7356670 |
Data processing system
A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit ( 18 a ) and a...
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7353337 |
Reducing cache effects of certain code pieces
Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since...
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7353371 |
Circuit to extract nonadjacent bits from data packets
A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination...
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7350059 |
Managing stack transfers in a register-based processor
The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers that...
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7343480 |
Single cycle context switching by swapping a primary latch value and a selected secondary latch value in a register file
A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to...
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7340591 |
Providing parallel operand functions using register file and extra path storage
A number of architectural and implementation approaches are described for using extra path (Epath) storage that operate in conjunction with a compute register file to obtain increased instruction...
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7337305 |
Method and pipeline architecture for processing multiple swap requests to reduce latency
A system and method of processing multiple swap requests including receiving a first swap request in a pipeline and executing the first swap request. A second swap request is also received in the...
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7330917 |
Decimation of fixed length queues having a number of position for holding data wherein new data is favored over old data
Decimation of data from a fixed length queue retaining a representative sample of the old data. Exponential decimation removes every nth sample. Dithered exponential decimation offsets the...
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7321964 |
Store-to-load forwarding buffer using indexed lookup
A microprocessor may include a dispatch unit configured to dispatch load and store operations and a load store unit configured to store information associated with load and store operations...
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7318014 |
Bit accurate hardware simulation in system level simulators
A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the...
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7318115 |
IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic
Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed...
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