Matches 501 - 550 out of 569 < 1 2 3 4 5 6 7 8 9 10 11 12 >
Match Document Document Title
5796996 Processor apparatus and its control method for controlling a processor having a CPU for executing an instruction according to a control program  
In the case where a CPU executes a write instruction of a control program for a memory mapped register of an external memory, a write address and write data are written into an output buffer,...
5790880 Microprocessor configured to dynamically connect processing elements according to data dependencies  
A microprocessor is provided which detects dependencies among instructions. The microprocessor assigns each instruction to a processing element or elements which perform the operation specified by...
5784645 Apparatus having a first microcomputer for reading first and second data from a non-volatile memory and processing the second data and transferring the first and second microcomputer  
An optical system including a first microcomputer having a first communication terminal and a second communication terminal, a second microcomputer having a third communication terminal which is...
5781790 Method and apparatus for performing floating point to integer transfers and vice versa  
A processor that performs integer-to-floating point transfers and vice versa using a store buffer in the processor to obviate the need for transferring data to memory and then back from memory. In...
5781787 Parallel program execution time with message consolidation  
In distributed memory multiprocessors, communication between processing elements (PEs) can have a significant impact on the overall computation time. In addition, contention for the communication...
5768551 Inter connected loop channel for reducing electrical signal jitter  
A fiber channel, interconnecting a plurality of disk drive loops and associated high speed bypass switches, has a selected group of high speed bypass switches to modularize the fiber channel and to...
5764942 Method and system for selective serialization of instruction processing in a superscalar processor system  
The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of...
5758195 Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register  
A data processing system including a data-memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data...
5758178 Miss tracking system and method  
A miss tracking system optimizes the bandwidth to a main memory that is associated with a processor that utilizes a data cache and that executes instructions out of order. The miss tracking system...
5751613 Persistent heap for dynamic picture objects  
There is provided a process control system having a display program that permits an program designer to create and edit dynamic picture objects in a persistent heap and save the heap to a storage...
5752269 Pipelined microprocessor that pipelines memory requests to an external memory  
Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock...
5729705 Method and apparatus for enhancing throughput of disk array data transfers in a controller  
A method for transferring data in a controller having a processor and a controller support device, with the controller connected to a host device and a disk drive. The method includes the steps of...
5717946 Data processor  
A data processor having a string operation instruction and a bit map operation instruction, and comprises a bus interface unit 157 which inputs/outputs data by the burst transfer function, and an...
5708843 Method and apparatus for handling code segment violations in a computer system  
A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking...
5696959 Memory store from a selected one of a register pair conditional upon the state of a selected status bit  
A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store...
5694588 Apparatus and method for synchronizing data transfers in a single instruction multiple data processor  
A synchronous vector processor (SVP) device (102) has a plurality of processing elements (150) which are comprised of an RF1 register (166), an ALU (164) and an RF0 (158). The processing elements...
5694572 Controllably operable method and apparatus for predicting addresses of future operand requests by examination of addresses of prior cache misses  
In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called...
5684983 Microprocessor executing multiple register transfer operations with a single instruction with derivation of destination register numbers from source register  
A microprocessor includes a register file that outputs data from multiple registers at one time, and that stores separate data to multiple registers at one time, and an instruction decoder for...
5685009 Shared floating-point registers and register port-pairing in a dual-architecture CPU  
A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex...
5649144 Apparatus, systems and methods for improving data cache hit rates  
A processing system is provided which generates a memory address and presents the memory address to a cache to retrieve corresponding data when such corresponding data is encached therein. The...
5615402 Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch  
A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory...
5608906 Multiple-task controller having a plurality of task memory input/output devices, input/output processing device, and a plurality of tasks controlled by external devices  
A multiple-task controller includes a plurality of tasks which are controlled with first and second external devices: task memory input/output devices provided respectively for the tasks; a serial...
5602998 Dequeue instruction in a system architecture for improved message passing and process synchronization  
A system and method for removing a queue entry containing message data from a queue shared by communicating, sequential processes includes dequeue (DEQ) and dequeue or wait (DEQW) instructions. The...
5590291 Digital signal processing system for limiting a result to be predetermined bit count  
A video codec (coder-decoder) system inputs consecutively admitted frames of sub-sampled video data obtained by sub-sampling video data in units of frames. The video data is coded in parallel by...
5542075 Method and apparatus for improving performance of out of sequence load operations in a computer system  
The invention provides for improved performance of out of sequence load operations. The system has an improved compiler, with an optimizer, an improved CPU with four new instructions in its...
5504868 SCSI command descriptor block parsing state machine  
A hard disk controller integrated circuit of a SCSI target device comprises a dedicated command descriptor block "CDB" parsing state machine. The dedicated CDB parsing state machine parses incoming...
5497468 Data processor that utilizes full data width when processing a string operation  
A data processor which performs in parallel a comparison process of n (which is an integer 2 or more)--sets first size data a elements by logical add operation between data elements in executing a...
5481736 Computer processing element having first and second functional units accessing shared memory output port on prioritized basis  
A processing element (42) design is provided for improving performance and reducing the number (30') of memory ports by eliminating the dedication of ports to specific functional units (22, 24, 26,...
5452428 Processor having different operand source information temporarily stored in plural holding registers to avoid using microprogram ROM capacity for such information  
An information processing apparatus executes a machine language instruction according to a microprogram controlling method. The apparatus comprises an instruction decoder for decoding the machine...
5426783 System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/390 instruction set  
A processing system comprising a first means for generating first signals indicating when the next instruction can begin processing where eight or less bytes are processed by the MOVE, PACK or...
5421029 Multiprocessor including system for pipeline processing of multi-functional instructions  
A data processor, comprises: an instruction decoding unit which includes an encoding circuit encoding bit positions of "1" or "0" of a register list field represented by a bit string consisting of...
5416911 Performance enhancement for load multiple register instruction  
In a pipeline processor, the identities of the highest and lowest numbered registers of a subset of general registers affected by a load multiple register (LMR) instruction are stored. The number...
5410682 In-register data manipulation for unaligned byte write using data shift in reduced instruction set processor  
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The...
5390307 Apparatus for a multi-data store or load instruction for transferring multiple contiguous storage locations in one transfer operation  
A data processor wherein, in the case where an instruction decoder has decoded a multi-data transfer (storing or loading) instruction, bits in a register list outputted from the instruction decoder...
5388235 Arithmetic and logic processor and operating method therefor  
An arithmetic and logic processor includes a register file structure wherein each procedure to be processed has assigned thereto a predetermined number of registers referred to as register window....
5367648 General purpose memory access scheme using register-indirect mode  
A memory access scheme achieved using a memory address register and a register-indirect memory accessing mode eliminates write back collisions, long cycle time, and enhances system performance....
5339429 Parallel processing system and compiling method used therefor  
A parallel processing system includes tightly coupled multiprocessors. Each multiprocessor incorporates a local extended storage device which is a secondary storage device for a main storage...
5305461 Method of transparently interconnecting message passing systems  
A method of passing data between objects located distributed among a plurality of virtual address space domains established by processes executing on a data processing system comprises several...
5293499 Apparatus for executing a RISC store and RI instruction pair in two clock cycles  
A processor for a SPARC based RISC computer including a central processing unit including a register file having a pair of read ports and a write port, an instruction register for holding an...
5278960 Information processing apparatus having detecting means for operand overlaps  
An information transfer apparatus for transferring memory operand data from a source address in a memory region to a destination address, including a first and second data overlap detecting...
5269008 Method and apparatus for pre-processing the source of a pop instruction in a pipeline computer  
A data processor which includes a pipeline processing unit that processes instructions, including a POP instruction. The POP instruction includes a destination operand field and has a stack top as...
5257386 Data transfer control system for virtual machine system  
A virtual machine system includes a storage for storing at least transfer priorities of virtual machines, a queuing part for making a queue of data transfer requests which request data transfers...
5187793 Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache  
An instruction caching system comprises meta-instructions which are contained within the program being executed. A meta-machine, which is a small segment of software, executes the meta-instructions...
5142633 Preprocessing implied specifiers in a pipelined processor  
An instruction decoder generates implied specifiers for certain predefined instructions, and an operand processing unit preprocess most of the implied specifiers in the same fashion as express...
5142635 Method and circuitry for performing multiple stack operations in succession in a pipelined digital computer  
A method for performing consecutive instructions to push data onto a stack in memory in a digital computer is described. During a first clock cycle, an instruction is decoded requiring a stack push...
5123093 Operational processor for performing a memory access and an operational process in parallel  
An operational processor comprising a data memory for storing data therein, at least one input data storage register for storing the data from the data memory, an arithmetic and logic unit (ALU)...
5027272 Method and apparatus for performing double precision vector operations on a coprocessor  
This invention relates to a system having a coprocessor being utilized by a processor for floating point double precision operations. The coprocessor utilizes one format for storing double...
4975835 Variable length data processing apparatus for consecutively processing variable-length data responsive to one instruction  
Data divided by delimiters representing the boundaries of the data is stored in a data memory. Instructions each including designation of a delimiter are stored in an instruction register. A...
4958275 Instruction decoder for a variable byte processor  
An instruction decoder, for a variable byte processor, is capable of making the variable byte processor operate at a high processing speed and high byte efficiency. The instruction decoder includes...
4930065 Automatic data channels for a computer system  
A data communications system for a computer for transferring data between the memory of the computer and one or more peripheral devices without requiring an interrupt context switch. The data...
Matches 501 - 550 out of 569 < 1 2 3 4 5 6 7 8 9 10 11 12 >