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7600100 Instruction encoding for system register bit set and clear  
An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the...
7581091 System and method for extracting fields from packets having fields spread over more than one register  
Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register...
7565515 Method and software for store multiplex operation  
A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register...
7558948 Method for providing zero overhead looping using carry chain masking  
A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at...
7543287 Using a block device interface to invoke device controller functionality  
In one embodiment, a standard block device command is received at a device controller. The standard block device command is addressed to a virtual block device associated with the device...
7529907 Method and apparatus for improved computer load and store operations  
Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by...
7526635 Programmable processor and system for store multiplex operation  
A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a...
7493481 Direct hardware processing of internal data structure fields  
In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code...
7480787 Method and structure for pipelining of SIMD conditional moves  
A mask is first generated in a general-purpose integer register. The mask is generated by executing a single instruction multiple data (SIMD) instruction on a plurality of operands stored in a...
7437541 Atomically updating 64 bit fields in the 32 bit AIX kernel  
A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an...
7404068 Single operation per-bit memory access  
Mechanisms for performing per-bit operations in system memory in a single operation thereby obviating the need for semaphore mechanisms when performing per-bit operations. A processor accesses an...
7401208 Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor  
A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream...
7401204 Parallel Processor efficiently executing variable instruction word  
A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information....
7373463 Antifraud method and circuit for an integrated circuit register containing data obtained from secret quantities  
An integrated circuit and an antifraud method implementing at least one operation involving at least one secret quantity, and functionally including upstream and downstream of the operator at least...
7370184 Shifter for alignment with bit formatter gating bits from shifted operand, shifted carry operand and most significant bit  
An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby...
7353501 Generic wrapper scheme  
A method instruments a function in an executable file so that the instrumented function calls a generic preprocessor prior to execution of the body of the function. After the preprocessor modifies...
7350058 Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register  
A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that...
7330937 Management of stack-based memory usage in a processor  
A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and...
7318014 Bit accurate hardware simulation in system level simulators  
A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the...
7302511 Chipset support for managing hardware interrupts in a virtual machine system  
In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to...
7290289 Processor with several calculating units  
A processor comprises a first calculating unit, a second calculating unit and a control means for controlling the two calculating units, such that they selectively operate in a high security mode...
7290122 Dataflow graph compression for power reduction in a vector processor  
A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each...
7278011 Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table  
A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive...
7275147 Method and apparatus for data alignment and parsing in SIMD computer architecture  
Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a...
7269720 Dynamically controlling execution of operations within a multi-operation instruction  
Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches...
7219213 Flag bits evaluation for multiple vector SIMD channels execution  
According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might...
7191317 System and method for selectively controlling operations in lanes  
A method and system for conditionally carrying out an operation defined in a computer instruction wherein a computer instruction is implemented on so-called packed operands; that is, operands...
7185183 Atomic update of CPO state  
A group of bit set and bit clear instructions are provided for a microprocessor to allow atomic modification of privileged architecture control registers. The bit set and bit clear instructions...
7143265 Computer program product memory access system  
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred...
7139904 Data byte insertion circuitry  
A data byte insertion circuit includes circuitry to generate derivative intermediate data words from input data words of a current and a preceding cycle, repositioning data bytes of the input data...
7114055 Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word  
A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean...
7028171 Multi-way select instructions using accumulated condition codes  
The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an...
7003653 Method for rapid interpretation of results returned by a parallel compare instruction  
A method for rapidly mapping a bitmask returned by a Single Instruction Multiple Data (SIMD) computer compare instruction is provided. A user supplied partitioned mapping variable includes multiple...
6968446 Flags handling for system call instructions  
A processor is configured to support a programmable flags masking during processing of a system call instruction such as Syscall. The processor includes a register storing a mask, where an...
6944753 Fixed point unit pipeline allowing partial instruction execution during the instruction dispatch cycle  
A method for allowing a partial instruction to be executed in a fixed point unit pipeline during the instruction dispatch cycle creates a mask used to select which bits of the operands participate...
6934828 Decoupling floating point linear address  
A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of...
6883087 Processing of binary data for compression  
Binary data is processed and organized by determining patterns specific for the binary data in a software package. Code sections may be split from an instruction according to the code section type...
6865644 System and method for industrial controller with an I/O processor using cache memory to optimize exchange of shared data  
A system and method for industrial control I/O forcing is provided. The invention includes a processor, shared memory and an I/O processor with cache memory. The invention provides for the cache...
6834337 System and method for enabling multiple signed independent data elements per register  
A system and method for data processing includes packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and simultaneously operating on...
6757820 Decompression bit processing with a general purpose alignment tool  
A method and apparatus for performing single-instruction bit field extraction and for counting a number of leading zeros in a sequence of bits on a general purpose processor are provided. The fast...
6757789 Apparatus and method for maximizing information transfers over limited interconnect resources  
The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to...
6748521 Microprocessor with instruction for saturating and packing data  
A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands and storing the separate saturated...
6745319 Microprocessor with instructions for shuffling and dealing data  
A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand ( 600 ) and storing the shuffled result in a selected...
6738792 Parallel mask generator  
A mask generator circuit includes at least first and second mask generator circuits coupled to receive most significant and least significant sections of the pointer and to generate masks...
6718456 Parallel pack instruction method and apparatus  
Disclosed herein is a apparatus and method for packing a 16-bit number into an 8-bit result byte. The method and apparatus utilize a parallel processing right shift circuit and a filter to obtain...
6715066 System and method for arranging bits of a data word in accordance with a mask  
A system is described for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having...
6691240 System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient way  
A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the...
6691222 Non-stalling circular counterflow pipeline processor with recorder buffer  
A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a...
6671797 Microprocessor with expand instruction for forming a mask from one bit  
A data processing system is provided with a digital signal processor which has an instruction for expanding one bit to form a mask field. In one form of the instruction, a first bit from a two-bit...
6658448 System and method for assigning processes to specific CPU's to increase scalability and performance of operating systems  
A method in a multi-processor computing system is disclosed. The method is an object-oriented method that allows a user to make associations between processes to be executed and available CPUs of...
Matches 1 - 50 out of 146 1 2 3 >