Matches 1 - 50 out of 352 1 2 3 4 5 6 7 8 >


Match Document Document Title
9015452 Vector math instruction execution by DSP processor approximating division and complex number magnitude  
A digital signal processor (DSP) includes an instruction fetch unit, an instruction decode unit, a register set and a plurality of work units in communication with the instruction decode unit. A...
9015453 Packing odd bytes from two source registers of packed data  
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data...
8984260 Predecode logic autovectorizing a group of scalar instructions including result summing add instruction to a vector instruction for execution in vector unit with dot product adder  
A circuit arrangement, method, and program product for substituting a plurality of scalar instructions in an instruction stream with a functionally equivalent vector instruction for execution by a...
8924693 Predicting a result for a predicate-generating instruction when processing vector instructions  
The described embodiments include a processor that executes vector instructions. While dispatching instructions at runtime, the processor encounters a predicate-generating instruction. Upon...
8909905 Method for performing plurality of bit operations and a device having plurality of bit operations capabilities  
A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted...
8880855 Dual register data path architecture with registers in a data file divided into groups and sub-groups  
A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of...
8838942 Multifunction hexadecimal instruction form system and program product  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
8838946 Packing lower half bits of signed data elements in two source registers in a destination register with saturation  
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data...
8793472 Vector index instruction for generating a result vector with incremental values based on a start value and an increment value  
The described embodiments include a processor that executes a vector instruction. The processor starts by receiving a start value and an increment value, and optionally receiving a predicate...
8788796 Technique for simulating floating-point stack operation involving conversion of certain floating-point register numbers based on a top-of-stack pointer and modulo function  
A Reduced Instruction Set Computing (RISC) processor is capable of emulating operation of a floating-point register stack. The RISC processor may include a floating-point register file containing...
8782376 Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic  
A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses...
8766991 Processing order with integer inputs and floating point inputs  
A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture values, then they may be processed by the...
8769249 Instructions with floating point control override  
Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, a processor includes a first logic to receive an instruction having one or more...
8769248 System and apparatus for group floating-point inflate and deflate operations  
Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and...
8683183 Performing a multiply-multiply-accumulate instruction  
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple...
8683182 System and apparatus for group floating-point inflate and deflate operations  
Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and...
8667250 Methods, apparatus, and instructions for converting vector data  
A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and...
8650383 Vector processing with predicate vector for setting element values based on key element position by executing remaining instruction  
The described embodiments include a processor that executes a vector instruction. The processor starts by receiving an input vector and optionally receiving a predicate vector as inputs. The...
8649508 System and method for implementing elliptic curve scalar multiplication in cryptography  
A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further...
8639914 Packing signed word elements from two source registers to saturated signed byte elements in destination register  
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data...
8583904 Processing vectors using wrapping negation instructions in the macroscalar architecture  
Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions...
8555037 Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture  
Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions...
8549265 Processing vectors using wrapping shift instructions in the macroscalar architecture  
Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions...
8539205 Processing vectors using wrapping multiply and divide instructions in the macroscalar architecture  
Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions...
8527742 Processing vectors using wrapping add and subtract instructions in the macroscalar architecture  
Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions...
8504805 Processor operating mode for mitigating dependency conditions between instructions having different operand sizes  
Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point...
8504806 Instruction for comparing active vector elements to preceding active elements to determine value differences  
The described embodiments include a processor that executes a ValueCheck instruction. In the described embodiments, the processor receives an input vector and a predicate vector, each including N...
8495602 Shader compile system and method  
The present disclosure includes a shader compiler system and method. In an embodiment, a shader compiler includes a decoder to translate an instruction having a vector representation to a unified...
8495343 Apparatus and method for detection and correction of denormal speculative floating point operand  
A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions...
8495342 Configuring plural cores to perform an instruction having a multi-core characteristic  
A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics...
8484443 Running multiply-accumulate instructions for processing vectors  
The described embodiments include RunningMAC1P and RunningMAC2P instructions. In the described embodiments, a processor receives a first input vector, a second input vector, a third input vector,...
8484266 Embedded control system with floating-point conversion  
An embedded control system capable of ensuring precision in arithmetic with data in the floating-point format and also avoiding a shortage of the storage area of a memory is provided. According to...
8478969 Performing a multiply-multiply-accumulate instruction  
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple...
8464031 Running unary operation instructions for processing vectors  
During operation, a processor generates a result vector. In particular, the processor records a value from an element at a key element position in an input vector into a base value. Next, for each...
8458444 Apparatus and method for handling dependency conditions between floating-point instructions  
Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may...
8447956 Running subtract and running divide instructions for processing vectors  
The described embodiments provide a processor for generating a result vector with subtracted or mathematically divided values from a first input vector. During operation, the processor receives...
8417921 Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector  
The described embodiments provide a processor for generating a result vector that contains results from a comparison operation. During operation, the processor receives a first input vector, a...
8392692 Determining index values for bits of binary vector by processing masked sub-vector index values  
In one embodiment, the present invention determines index values corresponding to bits of a binary vector that have a value of 1. During each clock cycle, a masking technique is applied to M...
8386756 Emulating hexadecimal floating-point operations in non-native systems  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
8386755 Non-atomic scheduling of micro-operations to perform round instruction  
A microprocessor executes an instruction specifying a floating-point input operand having a predetermined size and that instructs the microprocessor to round the floating-point input operand to an...
8364938 Running-AND, running-OR, running-XOR, and running-multiply instructions for processing vectors using a base value from a key element of an input vector  
In the described embodiments, a processor captures a value from an element at a key element position in a second input vector into a base value. The processor then generates a result vector by, if...
8359460 Running-sum instructions for processing vectors using a base value from a key element of an input vector  
The described embodiments provide a processor for generating a result vector with summed values from a first input vector. During operation, the processor receives the first input vector, a second...
8359461 Running-shift instructions for processing vectors using a base value from a key element of an input vector  
The described embodiments provide a processor for generating a result vector with shifted values. During operation, the processor receives a first input vector, a second input vector, and a...
8352528 Apparatus for efficient DCT calculations in a SIMD programmable processor  
The present invention relates to a efficient implementation of integer and fractional 8-length or 4-length, or 8×8 or 4×4 DCT in a SIMD processor as part of MPEG and other video compression standards.
8341204 Vector SIMD processor  
A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and...
8335912 Logical map table for detecting dependency conditions between instructions having varying width operand values  
Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used...
8327120 Instructions with floating point control override  
Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control...
8239439 Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessor  
Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises transferring more than two operands to...
8203567 Graphics processing method and apparatus implementing window system  
A graphics processing method and apparatus described herein is capable of converting graphics processing of a window system into a vector-based application program interface (API) format usable in...
8200948 Apparatus and method for performing re-arrangement operations on data  
An apparatus and method are provided for performing re-arrangement operations on data. The data processing apparatus has a register data store with a plurality of registers for storing data, and...

Matches 1 - 50 out of 352 1 2 3 4 5 6 7 8 >