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7600104 Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length  
System and method are provided for parallel vector data processing having a data processor capable of vector data having a defined first bit-length. In one embodiment, at least one of first and...
7574584 Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine  
In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The...
7565513 Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations  
A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and...
7558947 Method and apparatus for computing vector absolute differences  
Methods and apparatuses for computing an absolute difference of two vectors of numbers. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single...
7546443 Providing extended precision in SIMD vector arithmetic operations  
The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data...
7516308 Processor for performing group floating-point operations  
A system and method expands a source operand to a width greater than that of a general purpose register or a data path. Operands are provided substantially larger than the data path width of a...
7516307 Processor for computing a packed sum of absolute differences and packed multiply-add  
A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to...
7500084 Multifunction hexadecimal instruction form  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
7457941 Vector processing system  
A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the...
7437540 Complex domain floating point VLIW DSP with data/program bus multiplexer and microprocessor interface  
A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability....
7406589 Processor having efficient function estimate instructions  
High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different...
7395414 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions  
A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT...
7373489 Apparatus and method for floating-point exception prediction and recovery  
An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of...
7373488 Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values  
A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a...
7363478 Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index  
A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data...
7353364 Apparatus and method for sharing a functional unit execution resource among a plurality of functional units  
An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to...
7350057 Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction  
Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for...
7337307 Exception handling with inserted status check command accommodating floating point instruction forward move across branch  
A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a pipelined...
7302690 Method and apparatus for transparently sharing an exception vector between firmware and an operating system  
A method, apparatus and computer instructions for handling exception vectors by firmware. An exception vector is identified to form an identified exception vector when control is passed from an...
7299342 Complex vector executing clustered SIMD micro-architecture DSP with accelerator coupled complex ALU paths each further including short multiplier/accumulator using two's complement  
A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the...
7284117 Processor that predicts floating point instruction latency based on predicted precision  
A processor includes a prediction circuit and a floating point unit. The prediction circuit is configured to predict an execution latency of a floating point operation. The floating point unit is...
7254698 Multifunction hexadecimal instructions  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
7243217 Floating point unit with variable speed execution pipeline and method of operation  
A variable speed floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages capable of executing floating point operations in a series of sequential steps;...
7243216 Apparatus and method for updating a status register in an out of order execution pipeline based on most recently issued instruction information  
An apparatus and method is disclosed for updating a status register in an out of order execution pipeline. In one embodiment a dispatch unit in a floating point unit sets a MRI bit flag that...
7240184 Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations  
A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic...
7225323 Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines  
A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic...
7219213 Flag bits evaluation for multiple vector SIMD channels execution  
According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might...
7213128 Storing and transferring SIMD saturation history flags and data size  
A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a...
7212959 Method and apparatus for accumulating floating point values  
A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained....
7206920 Min/max value validation by repeated parallel comparison of the value with multiple elements of a set of data elements  
A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in...
7191316 Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream  
A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is...
7188233 System and method for performing floating point store folding  
A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a...
7167972 Vector/scalar system with vector unit producing scalar result from vector results according to modifier in vector instruction  
Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector...
7159100 Method for providing extended precision in SIMD vector arithmetic operations  
The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data...
7149882 Processor with instructions that operate on different data types stored in the same single logical register file  
A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical...
7107435 System and method for using hardware assist functions to process multiple arbitrary sized data elements in a register  
A system and method for processing multiple arbitrary sized data elements in a register. A method of the invention comprises the steps of: creating a mask register that defines a set of arbitrary...
7100026 System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values  
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output...
7099851 Applying term consistency to an equality constrained interval global optimization problem  
One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of equality constraints q 1 (x)=0 (i=1, . . . , r), wherein...
7058926 Tool for implementing Floating-Point related applications using customized language  
A tool for implementing a Floating-Point related application. The tool includes a receiver for receiving a list of commands in a computer language. The language defines Floating-Point events of...
7047179 Clustered processors in an emulation engine  
Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one...
7043516 Reduction of add-pipe logic by operand offset shift  
The shifters ( 30, 32 ) that a floating-point processor ( 10 )'s addition pipeline ( 14 ) uses to align or normalize floating-point operands' mantissas before addition or subtraction shift a given...
7039792 Method and system for implementing a floating point compare using recorded flags  
A method and system for implementing a floating point compare operation in an x86 compatible processor. The method includes the step of comparing a first bit pattern and a second bit pattern using...
7028066 Vector SIMD processor  
A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby...
6976153 Floating point unit with try-again reservation station and method of operation  
A floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages for executing floating point operations in a series of sequential steps; and 2) a try-again...
6973551 Data storage system having atomic memory operation  
A method and system for enabling a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations. The method includes...
6968445 Multithreaded processor with efficient processing for convergence device applications  
A multithreaded processor includes an instruction decoder for decoding retrieved instructions to determine an instruction type for each of the retrieved instructions, an integer unit coupled to the...
6961845 System to perform horizontal additions  
A method and apparatus for including in a processor instructions for performing intra-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored...
6954841 Viterbi decoding for SIMD vector processors with indirect vector element access  
A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal...
6934831 Power reduction mechanism for floating point register file reads  
A system and method for reducing power consumed by a floating unit performing iterative calculations in a loop through selectively inhibiting floating point register file reads. One or more source...
6934828 Decoupling floating point linear address  
A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of...
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