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6105129 Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction  
A microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats. In one embodiment, the registers are the floating point registers defined...
6094637 Fast MPEG audio subband decoding using a multimedia processor  
A decoding process for a MPEG1 audio subband uses the symmetry of filter coefficients to reduce the number of multiplications required to decode an audio subband. The decoding process can be...
6094719 Reducing data dependent conflicts by converting single precision instructions into microinstructions using renamed phantom registers in a processor having double precision registers  
In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision floating-point arithmetic operation having...
6061782 Mechanism for floating point to integer conversion with RGB bias multiply  
An apparatus and method for performing a floating point multiply (by a fixed graphics constant), and converting the product of the multiply into an integer, within a single operation is provided....
6055594 Byte accessible memory interface using reduced memory control pin count  
A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for...
6049865 Method and apparatus for implementing floating point projection instructions  
A floating point unit (60) capable of executing projection instructions provides performance improvement in multiple precision floating point arithmetic. The projection instructions provide for...
6047372 Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional...
6044454 IEEE compliant floating point unit  
IEEE compliant floating point unit mechanism allows variability in the execution of floating point operations according to the IEEE 754 standard and allowing variability of the standard to co-exist...
6035391 Floating point operation system which determines an exchange instruction and updates a reference table which maps logical registers to physical registers  
A system for processing a floating point instruction includes a stack, virtual registers, a stack pointer pointing to one of the virtual registers as top of stack, physical registers, and a...
6032249 Method and system for executing a serializing instruction while bypassing a floating point unit pipeline  
A method and system for providing direct execution of a serializing instruction in a processor is disclosed. The processor has the serializing instruction and a nonserializing instruction. The...
6029243 Floating-point processor with operand-format precision greater than execution precision  
A floating-point processor nominally capable of single and double, but not extended, precision execution stores operands in extended-precision format. A format converter converts single and double...
6026483 Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands  
A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and comprises a partial product...
6021488 Data processing system having an apparatus for tracking a status of an out-of-order operation and method thereof  
An FPSCR (Floating Point Status and Control Register) mechanism supports out-of-order floating point unit instruction execution. The FPSCR mechanism provides appropriate reporting of exceptions to...
6018756 Reduced-latency floating-point pipeline using normalization shifts of both operands  
If the exponents of a floating-point-processor addition pipeline's input operands are equal, a signal (INVERT) that determines whether the pipeline's sole full-width carry-propagate mantissa adder...
6014743 Apparatus and method for recording a floating point error pointer in zero cycles  
An apparatus and method for recording a floating point macro instruction error pointer within a microprocessor is provided. The apparatus includes translation/control logic for generating a micro...
6014736 Apparatus and method for improved floating point exchange  
A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes...
6012139 Microprocessor including floating point unit with 16-bit fixed length instruction set  
A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing....
6009511 Apparatus and method for tagging floating point operands and results for rapid detection of special floating point numbers  
A superscalar microprocessor appends a tag value to each floating point number. The tag value indicates whether the corresponding floating point number is a normal floating point number or a...
6009509 Method and system for the temporary designation and utilization of a plurality of physical registers as a stack  
A method and system in a superscalar data processing system are disclosed for the temporary designation and utilization of a plurality of physical registers as a stack. For each of the multiple...
5999893 Classification system and method using combined information testing  
A classification system uses sensors to obtain information from which feaes which characterized a source or object to classified can be extracted. The features are extracted from the information...
5995122 Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format  
A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit...
5987597 Data processor with execution control for first and second execution units  
An instruction fetcher reads out instructions and data from a memory. The instructions and data are decoded by an instruction decoder. When a data transfer instruction is fed to an input register...
5978901 Floating point and multimedia unit with data type reclassification capability  
A superscalar microprocessor includes a combination floating point and multimedia unit. The floating point and multimedia unit includes one set of registers. The multimedia core and floating point...
5974432 On-the-fly one-hot encoding of leading zero count  
A superscalar microprocessor including a floating point unit implements a floating point adder with a leading zero anticipator that predicts the number of leading zeros in the significand sum of...
5966528 SIMD/MIMD array processor with vector processing  
A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a...
5961636 Checkpoint table for selective instruction flushing in a speculative execution unit  
In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table...
5956494 Method, apparatus, and computer instruction for enabling gain control in a digital signal processor  
A digital signal processor (10) for implementing a gain instruction. The gain instruction, when decoded, controls a multiplexer (43) to select a gain control index signal. The value of the chosen...
5931943 Floating point NaN comparison  
A circuit for comparing and selecting NaN inputs is disclosed. Each NaN input is transformed by appending a sign bit to the end of a significand. In one particular embodiment, the inverse of the...
5926643 Data driven processor performing parallel scalar and vector processing  
A data driven data processing apparatus executes a data flow graph as a program for a plurality of processing elements arranged in a pipeline ring for transferring packets of scalar and vector...
5918062 Microprocessor including an efficient implemention of an accumulate instruction  
An execution unit configured to perform a plurality of arithmetic operations using the same set of operands. These operands include corresponding input vector values in each of a plurality of input...
5889984 Floating point and integer condition compatibility for conditional branches and conditional moves  
In a processor where separate integer and floating point units are utilized, conditions generated in the integer unit are transferred and made compatible for use in the floating point unit by...
5889980 Mode independent support of format conversion instructions for hexadecimal and binary floating point processing  
A computer system having multiple floating point modes and common instructions for each mode in order to implement operations in a mode independent manner. A computer system includes two floating...
5887160 Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor  
A microprocessor synchronously executes instructions, the instructions including integer instructions for performing integer operations and floating point instructions for performing real number...
5887185 Interface for coupling a floating point unit to a reorder buffer  
A microprocessor has an interface between a reorder buffer and a floating point unit, including a retire signal provided by the reorder buffer and a valid signal provided by the floating point...
5884070 Method for processing single precision arithmetic operations in system where two single precision registers are aliased to one double precision register  
In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision floating-point arithmetic operation having...
5859998 Hierarchical microcode implementation of floating point instructions for a microprocessor  
A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses...
5857089 Floating point stack and exchange instruction  
In a processor (110) that performs multiple instructions in a single cycle, predicts outcomes of branch conditions and speculatively executes instructions based on the branch predictions, a method...
5852726 Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner  
A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is...
5828873 Assembly queue for a floating point unit  
A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses...
5826070 Apparatus and method for maintaining status flags and condition codes using a renaming technique in an out of order floating point execution unit  
An apparatus and method reduces the number of rename registers for a floating point status and control register (FPSCR) in a superscalar microprocessor executing out of order/speculative...
5812823 Method and system for performing an emulation context save and restore that is transparent to the operating system  
A system and method for performing an emulation context switch save and restore in a processor that executes host applications and emulates guest applications. The processor includes an operating...
5812439 Technique of incorporating floating point information into processor instructions  
A floating point system and method employing instructions where instruction have incorporated floating point information. The floating point information indicates whether an exception trap should...
5809292 Floating point for simid array machine  
A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein...
5805874 Method and apparatus for performing a vector skip instruction in a data processor  
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single...
5805875 Vector processing system with multi-operation, run-time configurable pipelines  
A data processing system contains both a scalar processor and a vector processor. The vector processor contains a plurality of functional units, each of which contains a plurality of parallel...
5805916 Method and apparatus for dynamic allocation of registers for intermediate floating-point results  
The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction...
5802288 Integrated communications for pipelined computers  
This document describes a feature that can be added to existing pipelined architectures (such as RISC) to enhance packet based or message passing communications. The feature integrates the...
5787026 Method and apparatus for providing memory access in a processor pipeline  
The invention provides a method and apparatus for providing operand reads in a processor pipeline. According to one aspect of the invention, a method is described for executing an instruction in a...
5778247 Multi-pipeline microprocessor with data precision mode indicator  
The present invention recognizes that for most functional units, there will rarely be both single and double precision operations in the pipeline at the same time. Accordingly, the present...
5761105 Reservation station including addressable constant store for a floating point processing unit  
A reservation station with an addressable constant store enables the provision of floating point constants to arithmetic units in a floating point unit of a superscalar processor. Floating point...
Matches 151 - 200 out of 261 < 1 2 3 4 5 6 >