Matches 101 - 150 out of 261 < 1 2 3 4 5 6 >
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6463525 Merging single precision floating point operands  
Where it is desired to perform a double precision operation using single precision operands, first and second single precision operands are loaded into first and second respective rows of a...
6460135 Data type conversion based on comparison of type information of registers and execution result  
In a microprocessor, a type information comparator compares type information of an execution result of an instruction with type information of the type information register corresponding to the...
6446193 Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture  
A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second...
6430681 Digital signal processor  
In a digital signal processor having an improved arithmetic processing efficiency, there is provided in parallel a first ROM for storing branch commands and a second ROM for storing arithmetic...
6425055 Way-predicting cache memory  
An apparatus and method for accessing a cache memory. In a cache memory, an address is received that includes a set field and a partial tag field, the set field and the partial tag field together...
6425074 Method and apparatus for rapid execution of FCOM and FSTSW  
A microprocessor configured to rapidly execute floating point store status word (FSTSW) type instructions that are immediately preceded by floating point compare (FCOM) type instructions is...
6418529 Apparatus and method for performing intra-add operation  
Method and apparatus for including in a processor, instructions for performing intra-add operations on packed data. In one embodiment, an execution unit is coupled to a storage area. The storeage...
6412065 Status register associated with MMX register file for tracking writes  
A portion of an x86 microprocessor that supports MMX instructions provides a write tracking unit that tracks writes to a separately provided MMX register file, and updates a status register...
6408379 Apparatus and method for executing floating-point store instructions in a microprocessor  
An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an...
6405305 Rapid execution of floating point load control word instructions  
A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating...
6393555 Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit  
A microprocessor with a floating point unit configured to rapidly execute floating point compare (FCOMI) type instructions that are followed by floating point conditional move (FCMOV) type...
6385713 Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements  
An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized...
6385716 Method and apparatus for tracking coherence of dual floating point and MMX register files  
An apparatus and method for tracking coherence between distinct floating point and MMX register files in a microprocessor is provided. The apparatus keeps track of the last time a floating point or...
6381689 Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction  
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently...
6374345 Apparatus and method for handling tiny numbers using a super sticky bit in a microprocessor  
An apparatus and method for handling tiny numbers using a super sticky bit are provided. In response to detecting that a preliminary result of an instruction corresponds to a tiny number and an...
6370637 Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria  
A microprocessor with a floating point unit configured to efficiently allocate multi-pipeline executable instructions is disclosed. Multi-pipeline executable instructions are instructions that are...
6370639 Processor architecture having two or more floating-point status fields  
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main...
6366998 Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model  
The present invention generally relates to a hybrid VLIW-SIMD programming model for a digital signal processor. The hybrid programming model broadcasts a packet of information to a plurality of...
6363476 Multiply-add operating device for floating point number  
A floating point multiply-add operating device in which a critical path in an addition process of continuous multiply-add operations of floating point numbers is shortened to improve operation...
6343296 On-line reorganization in object-oriented databases  
An on-line reorganization method of an object-oriented database with physical references involves a novel fuzzy traversal of the database, or a partition thereof, to identify the approximate...
6339823 Method and apparatus for selective writing of incoherent MMX registers  
A dual register file MMX-type architecture comprises monitoring logic for identifying which registers in a register file have been written to. The monitoring logic is coupled to write-enable logic...
6338135 Data processing system and method for performing an arithmetic operation on a plurality of signed data values  
Disclosed is a data processing system and a method for performing an arithmetic operation on a plurality of signed data values. In the data processing system and the method, there is a first step...
6336183 System and method for executing store instructions  
In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address...
6321327 Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations  
A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple...
6317824 Method and apparatus for performing integer operations in response to a result of a floating point operation  
A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and...
6307553 System and method for performing a MOVHPS-MOVLPS instruction  
An apparatus and method for performing a MOVHPS-MOVLPS operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having a pair of data...
6301705 System and method for deferring exceptions generated during speculative execution  
The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and...
6298477 Method and apparatus for selecting ways to compile at runtime  
Apparatus, methods, and computer program products are disclosed for determining how to compile a program at runtime. A bytecode instruction associated with the program that can be compiled in...
6292886 Scalar hardware for performing SIMD operations  
A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the...
6275749 Interrupt-controlled thread processing  
Rapid thread processing is performed by associating thread contexts stored in a remote memory with interrupts for controlling the operation of a hardware-accelerated processor. This both minimizes...
6253312 Method and apparatus for double operand load  
An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic,...
6253299 Virtual cache registers with selectable width for accommodating different precision data formats  
A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual...
6247117 Apparatus and method for using checking instructions in a floating-point execution unit  
The use of checking instructions to detect special and exceptional cases of a defined data format in a microprocessor is disclosed. Generally speaking, a checking instruction is included with the...
6233672 Piping rounding mode bits with floating point instructions to eliminate serialization  
A floating point unit is provided which conveys the rounding mode in effect upon dispatch of a particular instruction with that particular instruction into the execution pipeline of the floating...
6233595 Fast multiplication of floating point values and integer powers of two  
A method for performing fast multiplication in a microprocessor is disclosed. The method comprises detecting multiplication operations that have a floating point operand and an integer operand,...
6226737 Apparatus and method for single precision multiplication  
An apparatus and method for performing single precision multiplication in a microprocessor are provided. The apparatus includes translation logic and extended precision floating point execution...
6219684 Optimized rounding in underflow handlers  
The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding...
6216222 Handling exceptions in a pipelined data processing apparatus  
A data processing apparatus and method is provided, the apparatus comprising an execution unit having a plurality of pipelined stages for executing instructions, such that a maximum of `n`...
6212539 Methods and apparatus for handling and storing bi-endian words in a floating-point processor  
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main...
6212627 System for converting packed integer data into packed floating point data in reduced time  
A method and apparatus for converting a packed integer data item having first and second data elements, to a packed floating-point data item. In one embodiment, a method includes moving the first...
6212618 Apparatus and method for performing multi-dimensional computations based on intra-add operation  
A method and apparatus for including in a processor, instructions for performing multiply-intra-add operations on packed data is described. In one embodiment, a processor is coupled to a memory....
6209083 Processor having selectable exception handling modes  
An FPU configured to operate in normal and fast modes. In normal mode, floating point instructions are stalled in an address calculation unit of the processor until the previously issued floating...
6195747 System and method for reducing data traffic between a processor and a system controller in a data processing system  
A system and method for reducing data traffic between the processor and the system controller in a data processing system during the execution of a vector or matrix instruction. When the processor...
6189094 Recirculating register file  
A floating point unit having a register bank containing a plurality of registers supports vector operations that execute a specified operation a plurality of times upon a sequence of data values...
6175912 Accumulator read port arbitration logic  
A processor architecture having an accumulator register file with multiple shared read and/or write ports. Depending on the instruction, each port can be used to communicate with a different data...
6170997 Method for executing instructions that operate on different data types stored in the same single logical register file  
A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that...
6167507 Apparatus and method for floating point exchange dispatch with reduced latency  
A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction....
6151669 Methods and apparatus for efficient control of floating-point status register  
A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main...
6148395 Shared floating-point unit in a single chip multiprocessor  
A single-chip multiprocessor (2, 102) is disclosed. The multiprocessor (2, 102) includes multiple central processing units, or CPUs, (10, 110) that share a floating-point unit (5, 105). The...
6112296 Floating point stack manipulation using a register map and speculative top of stack values  
A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of...
Matches 101 - 150 out of 261 < 1 2 3 4 5 6 >