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6931511 Parallel vector table look-up with replicated index element vector  
Methods and apparatuses for looking up vectors in parallel using vector table look up operations. In one aspect of the invention, a method to look up a plurality of data items indexed by a vector...
6922771 Vector floating point unit  
The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor...
6915411 SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath  
A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in...
6907518 Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same  
For use in a processor having a first number of decode units for decoding an ordered stream of floating point instructions, a floating point unit (FPU) for receiving decoded ones of the floating...
6892295 Processing architecture having an array bounds check capability  
According to the invention, a method for processing data related to an array of elements is disclosed. In one embodiment, a method for processing data related to an array of elements is disclosed....
6857061 Method and apparatus for obtaining a scalar value directly from a vector register  
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
6842850 DSP data type matching for operation using multiple functional units  
An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The ISA implemented with the ASSP, is adapted to DSP...
6834337 System and method for enabling multiple signed independent data elements per register  
A system and method for data processing includes packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and simultaneously operating on...
6829696 Data processing system with register store/load utilizing data packing/unpacking  
A data processing system (e.g., microprocessor 30 ) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor...
6826682 Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state  
A process which automatically inserts commands that test for raised exceptions indicating floating point status exceptions into a sequence of instructions to be executed, and responds to exceptions...
6792523 Processor with instructions that operate on different data types stored in the same single logical register file  
A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first...
6782470 Operand queues for streaming data: A processor register file extension  
The register file of a processor includes embedded operand queues. The configuration of the register file into registers and operand queues is defined dynamically by a computer program. The...
6779103 Control word register renaming  
A control word register, which is specified in a load control word instruction, is renamed and mapped into one of a plurality of physical control word registers. The renaming is performed by a...
6763451 Multiprocessor exchange provided with floating function  
In a multiprocessor exchange having a floating function, a signal distribution control processor is provided between a plurality of call control processors and a plurality of line controllers, and...
6757812 Leading bit prediction with in-parallel correction  
For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two...
6754810 Instruction set for bi-directional conversion and transfer of integer and floating point data  
An apparatus and method for bi-directional format conversion and transfer of data between integer and floating point registers is provided. A floating point register is configured to store floating...
6751725 Methods and apparatuses to clear state for operation of a stack  
Methods and apparatuses to clear state for operation of a stack. According to one embodiment of the invention, a processor comprises a set of one or more storage areas and a decode unit. The set of...
6748521 Microprocessor with instruction for saturating and packing data  
A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands and storing the separate saturated...
6735687 Multithreaded microprocessor with asymmetrical central processing units  
In addition to the normal circuitry which provides the normal computation, a microprocessor is provided with one or more additional but simplified central processing units which allows additional...
6728874 System and method for processing vectorized data  
A method and system for correctly processing both big endian and little endian vector data. If the vector has a little endian data order, each piece of data (such as a byte) within the vector is...
6728865 Pipeline replay support for unaligned memory operations  
Instructions asserted in a microprocessors instruction pipeline ( 3 ) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline ( 5 ) that...
6724759 System, method and article of manufacture for transferring a packet from a port controller to a switch fabric in a switch fabric chipset system  
A system, method and article of manufacture are provided for transferring a packet from a port controller to a switch fabric in a switch fabric system. Notification is received indicating that a...
6725361 Method and apparatus for emulating a floating point stack in a translation process  
A floating point processor including a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable...
6725354 Shared execution unit in a dual core processor  
A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for...
6715061 Multimedia-instruction acceleration device for increasing efficiency and method for the same  
The present invention proposes a multimedia-instruction acceleration device for increasing efficiency and a method for the same, which uses instruction strings having a floating-point value check...
6701427 Data processing apparatus and method for processing floating point instructions  
A data processing apparatus for processing floating point instructions is responsive to a floating point instruction to apply a floating point operation to a number of operands to produce a final...
6675286 Multimedia instruction set for wide data paths  
Partitioned sigma instructions are provided in which processor capacity is effectively distributed among multiple sigma operations which are executed concurrently. Special registers are included...
6675292 Exception handling for SIMD floating point-instructions using a floating point status register to report exceptions  
A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE...
6671796 Converting an arbitrary fixed point value to a floating point value  
A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an...
6668315 Methods and apparatus for exchanging the contents of registers  
A processor based computer system having dependency checking logic and a register stack, wherein the system overrides the dependency logic such that move instructions associated with the stack...
6651159 Floating point register stack management for CISC  
A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose...
6647486 Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and processing of routine data  
Routine processing for routine data, non-routine processing for routine data and general non-routine processing are to be processed efficiently. To this end, a main CPU has a CPU core having a...
6615341 Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control  
A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning...
6606700 DSP with dual-mac processor and dual-mac coprocessor  
The invention is a digital signal processor architecture that is designed to speed up frequently-used signal processing computations, such as FIR filters, correlations, FFTs, and DFTs. The...
6598149 Performance enhancement for code transitions of floating point and packed data modes  
A technique for enhancing performance for code transitions of floating point and packed data modes, in which a tag incorrect (TINC) bit is used to indicate a potential fault condition when...
6591361 Method and apparatus for converting data into different ordinal types  
A method and apparatus that converts integer numbers to/from floating point representations while loading/storing the data. The method and apparatus perform this conversion within a central...
6578059 Methods and apparatus for controlling exponent range in floating-point calculations  
A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main...
6571265 Mechanism to detect IEEE underflow exceptions on speculative floating-point operations  
A mechanism is disclosed for detecting underflow conditions for speculative floating-point operations. A floating-point status register includes a status flag which is set when a result generated...
6571386 Apparatus and method for program optimizing  
An optimizer ( 100 ) comprises a memory ( 110 ) and a processor ( 130 ). The memory stores a program ( 200 ) to be optimized and optimization software ( 301 ). Controlled by the optimization...
6557097 Linear vector computation  
A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient...
6553486 Context switching for vector transfer unit  
A vector transfer unit for handling transfers of vector data between a memory and a data processor by one or more application programs in a computer system. A compiler identifies the use of vector...
6546480 Instructions for arithmetic operations on vectored data  
A method is disclosed for effectuating multiplication in a processor core. The method supports multiplication instructions for two formats of data: integer-formatted data and fixed-point data,...
6542983 Microcomputer/floating point processor interface and method  
In a computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU execution pipeline including a CPU decoder pipestage and...
6519694 System for handling load errors having symbolic entity generator to generate symbolic entity and ALU to propagate the symbolic entity  
In a RISC or CISC processor supporting the IEEE 754 Not-a-Number (NaN) standard and of the kind comprising a load/store unit, a register unit and an arithmetic logic unit, and wherein the...
6519696 Paired register exchange using renaming register map  
An apparatus and method are provided for performing a floating point exchange operation in a pipeline microprocessor in zero effective clock cycles. The present invention exploits the pattern of...
6519695 Explicit rate computational engine  
A high speed programmable ER computational engine that is based on a micro-programmed control unit and a register intensive pipelined datapath that removes the need for having an instruction set...
6493817 Floating-point unit which utilizes standard MAC units for performing SIMD operations  
The present invention provides a method and apparatus for performing floating-point operations. The apparatus of the present invention comprises a floating point unit which comprises standard...
6487653 Method and apparatus for denormal load handling  
A microprocessor configured to dynamically switch its floating point load pipeline length from one stage in length to more than one stage in length is disclosed. The microprocessor may perform...
6484251 Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor  
A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky...
6477638 Synchronized instruction advancement through CPU and FPU pipelines  
A computer system having a central processing unit (CPU) execution pipeline and a floating point unit (FPU) execution pipeline, the CPU pipeline including a plurality of pipestages and the FPU...
Matches 51 - 100 out of 261 < 1 2 3 4 5 6 >