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9043581 Storing in other queue when reservation station instruction queue reserved for immediate source operand instruction execution unit is full  
A processing apparatus includes an execution unit which performs computation on two operand inputs each being selectable between read data from a register and an immediate value. The processing...
9015452 Vector math instruction execution by DSP processor approximating division and complex number magnitude  
A digital signal processor (DSP) includes an instruction fetch unit, an instruction decode unit, a register set and a plurality of work units in communication with the instruction decode unit. A...
9009723 Distributed acceleration devices management for streams processing  
A method for managing distributed computer data stream acceleration devices is provided that utilizes distributed acceleration devices on nodes within the computing system to process inquiries by...
8990767 Parallelization method, system and program  
A method, system, and article of manufacture for solving ordinary differential equations described in a graphical model with nodes as blocks and dependencies as links using the processing of a...
8984499 Methods to optimize a program loop via vector instructions using a shuffle table and a blend table  
According to one embodiment, a code optimizer is configured to receive first code having a program loop implemented with scalar instructions to store values of a first array to a second array...
8938607 Data packet arithmetic logic devices and methods  
New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs...
8914430 Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions  
A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second...
8909904 Combined byte-permute and bit shift unit  
A processor includes a decode unit and a byte permute unit. The byte permute unit receives an instruction from the decode unit. The byte permute unit determines whether the instruction corresponds...
8904152 Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture  
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with...
8880856 Efficient arithmetic logic units  
A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a...
8879670 Flexible channel decoder  
A configurable Turbo-LDPC decoder having A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of the decoding...
8874882 Compiler-directed sign/zero extension of a first bit size result to overwrite incorrect data before subsequent processing involving the result within an architecture supporting larger second bit size values  
Apparatus and methods to add an extended first bit size data item of a first source operand specified by an instruction to a second source operand specified by the instruction. The first source...
8831791 Processor cooling management  
Illustrative embodiments provide a computer implemented method, a data processing system, and a computer program product for adjusting cooling settings. The computer implemented method comprises...
8766991 Processing order with integer inputs and floating point inputs  
A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture values, then they may be processed by the...
8756270 Collective acceleration unit tree structure  
A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an...
8751655 Collective acceleration unit tree structure  
A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an...
8738893 Add instructions to add three source operands  
A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first,...
8732227 Method and processor unit for implementing a characteristic-2-multiplication  
The method for implementing a characteristic-2-multiplication of at least two input bit strings each having a number N of bits by means of a processor unit suitable for carrying out an integer...
8719589 Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key values  
A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS...
8700688 Polynomial data processing operation  
A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a...
8656143 Variable clocked heterogeneous serial array processor  
A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all...
8649508 System and method for implementing elliptic curve scalar multiplication in cryptography  
A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further...
8635415 Managing and implementing metadata in central processing unit using register extensions  
A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is...
8635434 Mathematical operation processing apparatus for performing high speed mathematical operations  
A mathematical operation processing apparatus is disclosed by which the supply of an operand which is performed based on condition codes by a plurality of mathematical operations can be performed...
8631224 SIMD dot product operations with overlapped operands  
A data processing system includes a plurality of general purpose registers, and processor circuitry for executing one or more instructions, including a vector dot product instruction for...
8627046 Data processing device  
A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects...
8610947 Image forming apparatus using logical arithmetic processing and image forming program using logical arithmetic processing  
An image processing apparatus includes an interpreting unit that interprets an order of the logical arithmetic processing and a kind of a logical arithmetic processing; and a drawing unit that, in...
8595470 DSP performing instruction analyzed m-bit processing of data stored in memory with truncation / extension via data exchange unit  
A digital signal processor includes an instruction analysis unit, a digital signal processor (DSP) core and a memory unit. The instruction analysis unit receives an instruction and determines the...
8589469 Bandwidth efficient instruction-driven multiplication engine  
Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local...
8583903 Helical band geometry for dynamical topology changing  
Disclosed herein are efficient geometries for dynamical topology changing (DTC), together with protocols to incorporate DTC into quantum computation. Given an Ising system, twisted depletion to...
8583902 Instruction support for performing montgomery multiplication  
Techniques are disclosed relating to a processor including instruction support for performing a Montgomery multiplication. The processor may issue, for execution, programmer-selectable instruction...
8566566 Vector processing of different instructions selected by each unit from multiple instruction group based on instruction predicate and previous result comparison  
There is provided a vector processing apparatus and method allowing for the parallel processing of a plurality of different instructions while maintaining vector processing architecture. The...
8560811 Lane crossing instruction selecting operand data bits conveyed from register via direct path and lane crossing path for execution  
The present invention provides a method and apparatus for handling lane-crossing instructions in an execution pipeline. One embodiment of the method includes conveying bits of an instruction from...
8549264 Add instructions to add three source operands  
A method in one aspect may include receiving an add instruction. The add instruction may indicate a first source operand, a second source operand, and a third source operand. A sum of the first,...
8543626 Method and apparatus for QR-factorizing matrix on a multiprocessor system  
A method and apparatus for QR-factorizing matrix on a multiprocessor system, wherein the multiprocessor system comprises at least one core processor and a plurality of accelerators, comprises the...
8520016 Instruction folding mechanism, method for performing the same and pixel processing system employing the same  
An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel...
8504807 Rotate instructions that complete execution without reading carry flag  
A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand...
8495734 Method and device for detecting an erroneous jump during program execution  
The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to...
8484440 Performing an allreduce operation on a plurality of compute nodes of a parallel computer  
Methods, apparatus, and products are disclosed for performing an allreduce operation on a plurality of compute nodes of a parallel computer, each node including at least two processing cores, that...
8473721 Video instruction processing of desired bytes in multi-byte buffers by shifting to matching byte location  
Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is...
8473719 Data packet arithmetic logic devices and methods  
New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs...
8468326 Method and apparatus for accelerating execution of logical “and” instructions in data processing applications  
A hardware module configured to perform single instructions faster than is possible in software running on the microprocessor. In one implementation, the hardware module is configured to perform a...
8447988 Hash processing using a processor  
In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance...
8429384 Interleaved hardware multithreading processor architecture  
An architecture for a digital signal processor alleviates the difficulties and complexities normally associated with writing and optimizing programs to avoid stalls during which one instruction...
8423748 Register control circuit and register control method  
A register control circuit that controls a register specified by an inputted address includes a signal output that outputs a first control signal and a second control signal based on the inputted...
8407273 Processing with compact arithmetic processing element  
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not...
8402254 Flag generation and use in processor with same processing for operation on small size operand as low order bits portion of operation on large size operand  
The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of...
8375197 Performing an allreduce operation on a plurality of compute nodes of a parallel computer  
Methods, apparatus, and products are disclosed for performing an allreduce operation on a plurality of compute nodes of a parallel computer, each node including at least two processing cores, that...
8311683 Processor cooling management  
Illustrative embodiments provide a computer implemented method, a data processing system, and a computer program product for adjusting cooling settings. The computer implemented method comprises...
8312442 Method and system for interprocedural prefetching  
A computing system has an amount of shared cache, and performs runtime automatic parallelization wherein when a parallelized loop is encountered, a main thread shares the workload with at least...

Matches 1 - 50 out of 426 1 2 3 4 5 6 7 8 9 >