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7631166 |
Processing instruction without operand by inferring related operation and operand address from previous instruction for extended precision computation
A repeat instruction (RPT) operates on one or more operands, but the RPT instruction includes only an opcode and does not specify locations of the operand or operands. The type of operation to be...
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7620764 |
System, apparatus and method for data path routing configurable to perform dynamic bit permutations
A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex...
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7590828 |
Processing a data word in a plurality of processing cycles
The invention relates to a processing of a data word in a plurality of processing cycles. In order to improve the efficiency of the processing, the data word is divided for each cycle into a...
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7587582 |
Method and apparatus for parallel arithmetic operations
A method and apparatus for efficiently performing graphic operations are provided. This is accomplished by providing a processor that supports any combination of the following instructions:...
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7555635 |
Data processing device
A data processing device has an instruction decoder ( 1 ), a control logic unit ( 3 ), and ALU ( 4 ). The instruction decoder ( 1 ) decodes instruction codes of an arithmetic instruction. The...
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7554464 |
Method and system for processing data having a pattern of repeating bits
A method and system allows for fast compression and decompressing of data using existing repetitive interleaved patterns within scientific data (floating point, integer, and image). An advantage of...
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7546443 |
Providing extended precision in SIMD vector arithmetic operations
The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data...
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7533249 |
Reconfigurable integrated circuit, circuit reconfiguration method and circuit reconfiguration apparatus
In order to reuse configuration information in a dynamic reconfiguration arithmetic circuit, data lines, address lines, a mask register and the like are required as hardware resources for rewriting...
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7525457 |
Transforming design objects in a computer by converting data sets between data set types
A computer implemented method converts a data set of a first type to a data set type of a second type. The method includes casting up a first data set of a first type to a prescribed data set type...
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7523261 |
Method and circuit arrangement for adapting a program to suit a buffer store
A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a...
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7502029 |
Instruction folding mechanism, method for performing the same and pixel processing system employing the same
An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel...
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7496736 |
Method of efficient digital processing of multi-dimensional data
An innovative approach for constructing optimum, high-performance, efficient DSP systems may include a system organization to match compute execution and data availability rate and to organize DSP...
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7475229 |
Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit
In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store....
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7464251 |
Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements
A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data...
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7457940 |
System and method for managing data
A system and method for managing data includes executing a set of instructions which are used for operating on compressed data and another set of instructions (e.g., different instructions) which...
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7454594 |
Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements
A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and...
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7447871 |
Data access program instruction encoding
A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit...
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7441106 |
Distributed processing in a multiple processing unit environment
Method and apparatus for performing distributed processing in a multi-processing unit environment. A first processing unit modifies a complex operation to provide an operational request packet...
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7434898 |
Computer system, computer program, and addition method
A computer system that makes it difficult to analyze the content of a calculation. In the computer system, a power operation unit performs the following operations using the input data “a” and...
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7434034 |
SIMD processor executing min/max instructions
The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage 24 , using SIMD at addressing techniques...
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7430656 |
System and method of converting data formats and communicating between execution units
A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural...
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7424594 |
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with...
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7409528 |
Digital signal processing architecture with a wide memory bandwidth and a memory mapping method thereof
A DSP (Digital Signal Processing) architecture with a wide memory bandwidth and a memory mapping method thereof. The DSP architecture includes: a first communication port; first, second, and third...
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7395302 |
Method and apparatus for performing horizontal addition and subtraction
A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory...
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7392368 |
Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements
Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate...
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7392275 |
Method and apparatus for performing efficient transformations with horizontal addition and subtraction
A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory...
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7389406 |
Apparatus and methods for utilization of splittable execution units of a processor
A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the...
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7366882 |
Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions
A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.
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7363471 |
Apparatus, system, and method of dynamic binary translation supporting a denormal input handling mechanism
A method may translate a set of source instructions into a set of target instructions, execute the set of target instructions, and unmask a denormal input control bit if the set of source...
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7353516 |
Data flow control for adaptive integrated circuitry
The present invention concerns data flow control in adaptive integrated circuitry which utilizes a data flow model for data processing. The present invention controls task initiation and execution...
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7346761 |
Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle
An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing...
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7343472 |
Processor having a finite field arithmetic unit utilizing an array of multipliers and adders
A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder. The instruction memory temporarily...
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7308560 |
Processing unit
A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for...
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7290121 |
Method and data processor with reduced stalling due to operand dependencies
A data processor ( 200 ) has a pipelined execution unit ( 120 ). Whether a first instruction is one of a class of instructions wherein as a result of execution of the first instruction the contents...
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7284117 |
Processor that predicts floating point instruction latency based on predicted precision
A processor includes a prediction circuit and a floating point unit. The prediction circuit is configured to predict an execution latency of a floating point operation. The floating point unit is...
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7269718 |
Method and apparatus for verifying data types to be used for instructions and casting data types if needed
A method, apparatus, and computer instructions in a processor for performing arithmetic operations. A data type associated with a particular memory location is used to determine if an operation...
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7249243 |
Control word prediction and varying recovery upon comparing actual to set of stored words
Techniques for control word prediction and speculative execution. In one embodiment, an apparatus includes a control word predictor, execution resources, and a comparison module. The control word...
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7240184 |
Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations
A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic...
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7237089 |
SIMD operation method and SIMD operation apparatus that implement SIMD operations without a large increase in the number of instructions
An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to...
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7237055 |
System, apparatus and method for data path routing configurable to perform dynamic bit permutations
A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex...
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7231510 |
Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof
A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue...
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7216138 |
Method and apparatus for floating point operations and format conversion operations
A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of...
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7216217 |
Programmable processor with group floating-point operations
A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction...
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7212959 |
Method and apparatus for accumulating floating point values
A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained....
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7206927 |
Pipelined processor method and circuit with interleaving of iterative operations
A method of executing an instruction stream in a pipelined execution unit of depth, p, comprises loading the instruction stream; detecting an iteration of an instruction in the loaded instruction...
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7191316 |
Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream
A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is...
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7159100 |
Method for providing extended precision in SIMD vector arithmetic operations
The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data...
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7149882 |
Processor with instructions that operate on different data types stored in the same single logical register file
A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical...
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7149877 |
Byte execution unit for carrying out byte instructions in a processor
A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands,...
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7146491 |
Apparatus and method for generating constant values
A data processing apparatus and method for generating constant values is provided. The data processing apparatus comprises a data processing unit operable in response to an instruction to perform a...
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