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9009506 Energy efficient microprocessor platform based on instructional level parallelism  
Embodiments of a processing architecture are described. The architecture includes a fetch unit for fetching instructions from a data bus. A scheduler receives data from the fetch unit and creates a...
9003169 Systems and methods for indirect register access using status-checking and status-setting instructions  
The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend...
9003420 Resolving RCU-scheduler deadlocks  
A technique for resolving deadlocks between an RCU subsystem and an operating system scheduler. An RCU reader manipulates a counter when entering and exiting an RCU read-side critical section. At...
9003170 Bit range isolation instructions, methods, and apparatus  
Receiving an instruction indicating a source operand and a destination operand. Storing a result in the destination operand in response to the instruction. The result operand may have: (1) first...
8997065 Automatic modularization of source code  
A device creates a graph based on source code, and analyzes the source code to identify private variables and functions of the source code and public variables and functions of the source code. The...
8997110 Resolving RCU-scheduler deadlocks  
A technique for resolving deadlocks between an RCU subsystem and an operating system scheduler. An RCU reader manipulates a counter when entering and exiting an RCU read-side critical section. At...
8990819 Efficient rollback and retry of conflicted speculative threads using distributed tokens  
A method for rolling back speculative threads in symmetric-multiprocessing (SMP) environments is disclosed. In one embodiment, such a method includes detecting an aborted thread at runtime and...
8977815 Control of entry of program instructions to a fetch stage within a processing pipepline  
A processing pipeline 6, 8, 10, 12 is provided with a main query stage 20 and a fetch stage 22. A buffer 24 stores program instructions which have missed within a cache memory 14. Query generation...
8972769 Data processing apparatus and control method for controlling clock frequency based on calculated frequency-to-response-time ratios  
A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the...
8972702 Systems and methods for power management in a high performance computing (HPC) cluster  
Embodiments of the invention broadly contemplate systems, methods, apparatuses and program products providing a power management technique for an HPC cluster with performance improvements for...
8972994 Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environment  
Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object...
8972703 Multithreaded processor architecture with operational latency hiding  
A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is dis...
8972704 Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory  
A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by...
8973006 Circuit arrangement for execution planning in a data processing system  
A circuit arrangement and method for a data processing system for executing a plurality of tasks with a central processing unit having a processing capacity allocated to the processing unit; the...
8966226 State machine for monitoring a trace port and verifying proper execution of a secure mode entry sequence instruction  
A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a...
8966461 Vector width-aware synchronization-elision for vector processors  
A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent...
8959339 Method and system for preventing unauthorized processor mode switches  
A system comprising a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple...
8959517 Cancellation mechanism for cancellable tasks including stolen task and descendent of stolen tasks from the cancellable taskgroup  
A scheduler in a process of a computer system schedules tasks of a task group for concurrent execution by multiple execution contexts. The scheduler provides a mechanism that allows the task group...
8959315 Multithreaded processor with multiple concurrent pipelines per thread  
A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of...
8954938 Managing build variants in a common repository  
A system includes determination of first coordinates in a repository coordinate system associated with a seed component corresponding to a target build result of a first code building system, the...
8954986 Systems and methods for data-parallel processing  
Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of...
8954497 Parallel distributed processing method and computer system  
Provided is a parallel distributed processing method executed by a computer system comprising a parallel-distributed-processing control server, a plurality of extraction processing servers and a...
8949582 Changing a flow identifier of a packet in a multi-thread, multi-flow network processor  
Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A packet classification...
8938606 System, apparatus, and method for segment register read and write regardless of privilege level  
Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the...
8930681 Enhancing performance by instruction interleaving and/or concurrent processing of multiple buffers  
An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first...
8924898 System and method of designing instruction extensions to supplement an existing processor instruction set architecture  
An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set,...
8924692 Event counter checkpointing and restoring  
A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the...
8918623 Implementing instruction set architectures with non-contiguous register file specifiers  
There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code...
8914618 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource  
In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous...
8914619 High-word facility for extending the number of general purpose registers available to instructions  
A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access...
8909903 Providing data to registers between execution stages  
In some implementations, a processor is provided having a buffer to store one or more instructions, a decoder configured to decode the one or more instructions and generate one or more decoded...
8910181 Divided central data processing  
A circuit configuration for a data processing system and a corresponding method for executing multiple tasks by way of a central processing unit having a processing capacity assigned to the...
8910177 Dynamic mapping of logical cores  
A processor that dynamically remaps logical cores to physical cores is disclosed. In one embodiment, the processor includes a plurality of physical cores, and is configured to store a mapping of...
8904151 Method and apparatus for the dynamic identification and merging of instructions for execution on a wide datapath  
A processing system and method includes a predecoder configured to identify instructions that are combinable. Instruction storage is configured to merge instructions that are combinable by...
8898396 Software pipelining on a network on chip  
Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface control...
8898438 Processor architecture for use in scheduling threads in response to communication activity  
The invention provides a processor comprising an execution unit for executing multiple threads, each thread comprising a sequence of instructions and each thread being designated to handle activity...
8892841 Store handling in a processor  
In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one...
8893094 Hardware compilation and/or translation with fault detection and roll back functionality  
Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes...
8886918 Dynamic instruction execution based on transaction priority tagging  
A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and...
8887156 Parallel processing of data  
An untrusted application is received at a data center including one or more processing modules and providing a native processing environment. The untrusted application includes a data parallel...
8886919 Remote update programming idiom accelerator with allocated processor resources  
A data processing system comprises at least one processing unit, a virtualization layer, and a remote update programming idiom accelerator. The remote update programming idiom accelerator is...
8880855 Dual register data path architecture with registers in a data file divided into groups and sub-groups  
A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a...
8880853 CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock  
A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is spinning on a lock. The wake-and-go...
8880854 Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register  
An out-of-order execution microprocessor executes an architectural segment register-loading instruction that instructs the microprocessor to load a new value into an architectural segment register...
8874881 Processors operable to allow flexible instruction alignment  
Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch...
8868886 Task switch immunized performance monitoring  
A performance monitoring technique provides task-switch immune operation without requiring storage and retrieval of the performance monitor state when a task switch occurs. When a hypervisor...
8856498 Prefetch request circuit  
A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among...
8850165 Method and apparatus for assigning thread priority in a processor or the like  
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further...
8850436 Opcode-specified predicatable warp post-synchronization  
One embodiment of the present invention sets forth a technique for performing a method for synchronizing divergent executing threads. The method includes receiving a plurality of instructions that...
8850446 System and method for using a task starvation indication to prevent starvations of tasks in a multiple processing entity system  
A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility...