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8438368 |
Processing apparatus, processing system, and computer readable medium
Optimizing processing of a document sequentially processed by a plurality of image processing apparatuses that refer to an instruction document indicating the processing to be performed by each of...
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8438568 |
Speculative thread execution with hardware transactional memory
In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self...
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8438369 |
Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor
A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each...
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8433884 |
Multiprocessor
A multiprocessor executes a plurality of threads without decreasing execution efficiency. The multiprocessor includes a first processor allocating a different register file to each of a...
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8429656 |
Thread count throttling for efficient resource utilization
Methods and apparatuses are presented for graphics operations with thread count throttling, involving operating a processor to carry out multiple threads of execution of, wherein the processor...
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8429386 |
Dynamic tag allocation in a multithreaded out-of-order processor
Various techniques for dynamically allocating instruction tags and using those tags are disclosed. These techniques may apply to processors supporting out-of-order execution and to architectures...
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8423605 |
Parallel distributed processing method and computer system
Provided is a parallel distributed processing method executed by a computer system comprising a parallel-distributed-processing control server, a plurality of extraction processing servers and a...
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8423750 |
Hardware assist thread for increasing code parallelism
Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a...
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8416430 |
Information processing apparatus
Disclosed is an information processing apparatus in which various kinds of information are processed in either the real time processing mode or the non-real time processing mode. The apparatus...
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8417920 |
Management of speculative transactions
Circuitry for receiving transaction requests from a plurality of masters and the masters themselves are disclosed. The circuitry comprises: an input port for receiving said transaction requests, at...
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8417735 |
Instruction-efficient algorithm for parallel scan using initialized memory regions to replace conditional statements
One embodiment of the present invention sets forth a technique for performing a parallel scan operation with high computational efficiency in a single-instruction multiple-data (SIMD) environment....
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8407455 |
Coexistence of advanced hardware synchronization and global locks
A computer-implemented method and article of manufacture is disclosed for enabling computer programs utilizing hardware transactional memory to safely interact with code utilizing traditional...
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8407451 |
Method and apparatus for enabling resource allocation identification at the instruction level in a processor system
An information handling system includes a processor with multiple hardware units that generate program application load, store, and I/O interface requests to system busses within the information...
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8402253 |
Managing multiple threads in a single pipeline
In one embodiment, the present invention includes a method for determining if an instruction of a first thread dispatched from a first queue associated with the first thread is stalled in a...
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8392932 |
Information processing device for causing a processor to context switch between threads including storing contexts based on next thread start position
An information processing device for causing a processor to execute a plurality of threads by switching between them. Each thread performs a process in correspondence with an obtainment of an...
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8392693 |
Fast REP STOS using grabline operations
A microprocessor includes a cache memory and a grabline instruction. The grabline instruction specifies a memory address that implicates a cache line of the memory. The grabline instruction...
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8392171 |
Register mapping in emulation of a target system on a host system
Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based...
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8387053 |
Method and system for enhancing computer processing performance
A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled...
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8380964 |
Processor including age tracking of issue queue instructions
An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue...
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8380965 |
Channel-based runtime engine for stream processing
An apparatus to facilitate design of a stream processing flow that satisfies an objective, wherein the flow includes at least three processing groups, wherein a first processing group includes a...
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8370607 |
Power efficient system for recovering an architecture register mapping table
A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an...
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8370576 |
Cache rollback acceleration via a bank based versioning cache ciruit
An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the...
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8370606 |
Switching data pointers based on context
Apparatus and methods for quickly switching active context between data pointer registers are disclosed. The apparatus can include a first register operable for storing a first data pointer and a...
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8370608 |
Copy-propagate, propagate-post, and propagate-prior instructions for processing vectors
The described embodiments provide a processor for generating a result vector with copied or propagated values from an input vector. During operation, the processor receives at least one input...
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8365177 |
Dynamically monitoring and rebalancing resource allocation of monitored processes based on execution rates of measuring processes at multiple priority levels
Measuring processes are started at a plurality of priority levels. A different one of the measuring processes is started for each of the priority levels. Subsequently, for each of the measuring...
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8359459 |
Using hardware support to reduce synchronization costs in multithreaded applications
A processor configured to synchronize threads in multithreaded applications. The processor includes first and second registers. The processor stores a first bitmask in the first register and a...
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8359457 |
Semiconductor device and data processing method performed by semiconductor device to perform a repeat operation within a reconfigurable pipeline
The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of...
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8356166 |
Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers
Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM...
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8356163 |
SIMD microprocessor and method for controlling variable sized image data processing
A disclosed SIMD microprocessor includes plural processor elements each having n arithmetic circuits and n registers configured to temporarily store data pieces to be input to the arithmetic...
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8356162 |
Execution unit with data dependent conditional write instructions
An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional...
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8356164 |
Shift-in-right instructions for processing vectors
The described embodiments provide a processor for generating a result vector with shifted values from an input vector. During operation, the processor receives an input vector and a control vector....
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8352711 |
Coordinating chores in a multiprocessing environment using a compiler generated exception table
The coordination and execution of chores in a multiprocessing environment. The coordination of chores is accomplished utilizing a compiler generated correlation that relates blocks of code that...
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8335911 |
Dynamic allocation of resources in a threaded, heterogeneous processor
Systems and methods for efficient dynamic utilization of shared resources in a processor. A processor comprises a front end pipeline, an execution pipeline, and a commit pipeline, wherein each...
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8332619 |
Primitives to enhance thread-level speculation
A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with...
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8332618 |
Out-of-order X86 microprocessor with fast shift-by-zero handling
An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of...
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8327379 |
Method for switching a selected task to be executed according with an output from task selecting circuit
A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory...
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8327119 |
Apparatus and method for executing fast bit scan forward/reverse (BSR/BSF) instructions
An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector...
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8321579 |
System and method for analyzing streams and counting stream items on multi-core processors
Systems and methods for parallel stream item counting are disclosed. A data stream is partitioned into portions and the portions are assigned to a plurality of processing cores. A sequential kernel...
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8316218 |
Look-ahead wake-and-go engine with speculative execution
A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicate that the thread is waiting...
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8316219 |
Synchronizing commands and dependencies in an asynchronous command queue
Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command...
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8312455 |
Optimizing execution of single-threaded programs on a multiprocessor managed by compilation
A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable...
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8312252 |
Content receiving apparatus and method, storage medium, and server
A content receiver is compatible with a plurality of rights management and protection methods (RMP) devised for each content distribution system. Only the format which specifies the specification...
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8307116 |
Scalable bus-based on-chip interconnection networks
The present disclosure generally relates to systems for routing data across a multinodal network. Example systems include a multinodal array having a plurality of nodes and a plurality of physical...
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8301868 |
System to profile and optimize user software in a managed run-time environment
Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture...
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8299816 |
Data processing apparatus
A data processing apparatus includes a reconfigurable circuit capable of reconfigurating partially a circuit configuration: and a reconfiguration controlling unit that controls a reconfiguration of...
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8296550 |
Hierarchical register file with operand capture ports
A hierarchical register file included in a hierarchical microprocessor that includes a plurality of execution clusters. An embodiment of the a hierarchical register file includes a first-level...
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8291198 |
Apparatus and method for regulating bursty data in a signal processing pipeline
Apparatus and method for regulating data in a signal processing pipeline are disclosed. For example, an apparatus is disclosed that includes a first element operable to determine a time interval...
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8291196 |
Forward-pass dead instruction identification and removal at run-time
Apparatuses and methods for dead instruction identification are disclosed. In one embodiment, an apparatus includes an instruction buffer and a dead instruction identifier. The instruction buffer...
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8285971 |
Block driven computation with an address generation accelerator
A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least...
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8281106 |
Specifying an addressing relationship in an operand data structure
A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least...
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