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8850165 Method and apparatus for assigning thread priority in a processor or the like  
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further...
8850436 Opcode-specified predicatable warp post-synchronization  
One embodiment of the present invention sets forth a technique for performing a method for synchronizing divergent executing threads. The method includes receiving a plurality of instructions that...
8850446 System and method for using a task starvation indication to prevent starvations of tasks in a multiple processing entity system  
A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility...
8838940 CPU utilization metering on systems that include multiple hardware threads per core  
Indicating usage in a system is disclosed. Indicating includes obtaining active thread information related to a number of hardware threads in a processor core, combining the active thread...
8838941 Multi-thread processors and methods for instruction execution and synchronization therein and computer program products thereof  
Methods for instruction execution and synchronization in a multi-thread processor are provided, wherein in the multi-thread processor, multiple threads are running and each of the threads can...
8832325 Transfer between storage devices  
Migrating data from a source storage device to a target storage device includes creating new paths to the target storage device, setting the target storage device to a state where I/O operations...
8826299 Spawned message state determination  
According to embodiments of the invention, methods and apparatus are provided for tracking the status or state of a message spawned or sent from one processing element to another processing element...
8825989 Technique to perform three-source operations  
A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than...
8819397 Processor with increased efficiency via control word prediction  
Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction...
8819399 Predicated control flow and store instructions for native code module security  
Some embodiments provide a system that executes a native code module. During operation, the system obtains the native code module. Next, the system loads the native code module into a secure...
8797868 Energy-efficient network device with coordinated scheduling and rate control using non-zero base power  
A network device of a communication network is configured to implement coordinated scheduling and processor rate control. In one aspect, packets are received in the network device and scheduled for...
8793689 Redundant multithreading processor  
A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant...
8793469 Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulation  
A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one...
8789065 System and method for input data load adaptive parallel processing  
Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of...
8788795 Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors  
A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is...
8782378 Dynamic instruction splitting  
A data processing apparatus and method are provided. The data processing apparatus is configured to perform data processing operations in response to data processing instructions including a...
8773455 RGB-out dither interface  
A display controller may include an RGB Interface module and a display port module, which may both use a target-master interface, in which the data receiving module pops pixels from the data...
8775778 Use of a helper thread to asynchronously compute incoming data  
A set of helper thread binaries is created from a set of main thread binaries. The helper thread monitors software or hardware ports for incoming data events. When the helper thread detects an...
8768642 System and method for remotely configuring semiconductor functional circuits  
The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional...
8769539 Scheduling scheme for load/store operations  
A method and apparatus are provided to control the order of execution of load and store operations. Also provided is a computer readable storage device encoded with data for adapting a...
8763002 Method, system, and apparatus for task allocation of multi-core processor  
A system for task allocation of a multi-core processor is provided. The system includes a task allocator and a plurality of sub-processing systems. Each of the sub-processing systems comprises a...
8762320 State machine with out-of-order processing functionality and method thereof  
According to one embodiment of the invention, software operating as a state machine may be implemented within a digital device to support out-of-ordering processing of events by the state machine....
8762690 Increment-propagate and decrement-propagate instructions for processing vectors  
The described embodiments provide a processor for generating a result vector with incremented or decremented values from an input vector. During operation, the processor receives an input vector...
8754896 Data processing apparatus having a parallel processing circuit including a plurality of processing modules, and method for controlling the same  
In an apparatus which includes a plurality of processing modules connected via a ring-shape bus, if a plurality pieces of pipeline processing to be processed in a different order is allocated to a...
8751774 Method and system for controlling message traffic between two processors  
A system and method for controlling messaging between a first processor and a second processor is disclosed. The second processor controls one or more peripheral devices on behalf of a plurality of...
8751833 Data processing system  
A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing...
8738892 Very long instruction word (VLIW) computer having efficient instruction code format  
A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a...
8725992 Programming language exposing idiom calls to a programming idiom accelerator  
A programming language may include hint instructions that may notify a programming idiom accelerator that a programming idiom is coming. An idiom begin hint exposes the programming idiom to the...
8725961 Systems, methods, and devices for configuring a device  
Disclosed are methods and devices, among which is a method for configuring an electronic device. In one embodiment, an electronic device may include one or more memory locations having stored...
8725993 Thread transition management  
Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the...
8719554 Scaleable status tracking of multiple assist hardware threads  
A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread...
8719553 Method for re-circulating a fragment through a rendering pipeline  
A microprocessor pipeline arrangement 1 includes a plurality of functional units 2, 3, 4, 5 and 6. Each functional unit 2, 3, 4, 5, 6 also has access to a respective cache memory 7, 8, 9, 10, 11....
8717586 Image processing apparatus that performs processing according to instruction defining the processing, control method for the apparatus, and storage medium  
An image processing apparatus which makes it possible to select a plurality of instructions at a time, and connect a plurality of documents together so that they can be processed as one document....
8713289 Efficiently emulating computer architecture condition code settings without executing branch instructions  
Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of...
8713294 Heap/stack guard pages using a wakeup unit  
A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes...
8713290 Scaleable status tracking of multiple assist hardware threads  
A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread...
8713335 Parallel processing computer systems with reduced power consumption and methods for providing the same  
A parallel processing computing system includes an ordered set of m memory banks and a processor core. The ordered set of m memory banks includes a first and a last memory bank, wherein m is an...
8713575 Scalable packet processing systems and methods  
A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data...
8707016 Thread partitioning in a multi-core environment  
A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to...
8700887 Register, processor, and method of controlling a processor using data type information  
A processor and a processor control method which efficiently perform an operation on data using a register, are provided. The register may include a data type field and a data field. The processor...
8700884 Single-instruction multiple-data vector permutation instruction and method for performing table lookups for in-range index values and determining constant values for out-of-range index values  
A processor in a data processing system executes a permutation instruction which identifies a first source register, at least one other source register, and a destination register. The first source...
8689222 Controlling priority of multi-threaded hardware resources by system calls  
A method, a system and a computer program product for controlling the hardware priority of hardware threads in a data processing system. A Thread Priority Control (TPC) utility assigns a primary...
8683181 Processor and method for distributing load among plural pipeline units  
An arithmetic processor includes a first pipeline unit configured to execute a first instruction that is input; a second pipeline unit configured to execute a second instruction that is input; a...
8677102 Instruction fusion calculation device and method for instruction fusion calculation  
An instruction fusion calculation device of the present invention includes an instruction fusion detection circuit, an instruction fusion circuit, and a calculator. The instruction fusion detection...
8676841 Detection of recurring non-occurrences of events using pattern matching  
Techniques for detecting recurring non-occurrences of an event. In one embodiment, techniques are provided for detecting the non-occurrence of an event within each of a series of time periods...
8677362 Apparatus for reconfiguring, mapping method and scheduling method in reconfigurable multi-processor system  
Provided are an apparatus for reconfiguring a mapping method and a scheduling method in a reconfigurable multi-processor system. A single function is mapped to a reconfigurable processor. When a...
8671232 System and method for dynamically migrating stash transactions  
A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output...
8671268 Apparatus and method for configurable processing  
A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more...
8671267 Monitoring processing time in a shared pipeline  
A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction...
8661230 Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions  
A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from...