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8700887 Register, processor, and method of controlling a processor using data type information  
A processor and a processor control method which efficiently perform an operation on data using a register, are provided. The register may include a data type field and a data field. The processor...
8700884 Single-instruction multiple-data vector permutation instruction and method for performing table lookups for in-range index values and determining constant values for out-of-range index values  
A processor in a data processing system executes a permutation instruction which identifies a first source register, at least one other source register, and a destination register. The first source...
8689222 Controlling priority of multi-threaded hardware resources by system calls  
A method, a system and a computer program product for controlling the hardware priority of hardware threads in a data processing system. A Thread Priority Control (TPC) utility assigns a primary...
8683181 Processor and method for distributing load among plural pipeline units  
An arithmetic processor includes a first pipeline unit configured to execute a first instruction that is input; a second pipeline unit configured to execute a second instruction that is input; a...
8677102 Instruction fusion calculation device and method for instruction fusion calculation  
An instruction fusion calculation device of the present invention includes an instruction fusion detection circuit, an instruction fusion circuit, and a calculator. The instruction fusion detection...
8676841 Detection of recurring non-occurrences of events using pattern matching  
Techniques for detecting recurring non-occurrences of an event. In one embodiment, techniques are provided for detecting the non-occurrence of an event within each of a series of time periods...
8677362 Apparatus for reconfiguring, mapping method and scheduling method in reconfigurable multi-processor system  
Provided are an apparatus for reconfiguring a mapping method and a scheduling method in a reconfigurable multi-processor system. A single function is mapped to a reconfigurable processor. When a...
8671232 System and method for dynamically migrating stash transactions  
A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output...
8671268 Apparatus and method for configurable processing  
A configurable execution unit comprises operators capable of being dynamically configured by an instruction at the level of processing multi-bit operand values. The unit comprises one or more...
8671267 Monitoring processing time in a shared pipeline  
A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction...
8661230 Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions  
A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from...
8656400 Synchronisation of execution threads on a multi-threaded processor  
Method and apparatus are provided for a synchronizing execution of a plurality of threads on a multi-threaded processor. Each thread is provided with a number of synchronization points...
8649508 System and method for implementing elliptic curve scalar multiplication in cryptography  
A system and method for implementing the Elliptic Curve scalar multiplication method in cryptography, where the Double Base Number System is expressed in decreasing order of exponents and further...
8650384 Method and system for dynamically parallelizing application program  
Provided is a method and system for dynamically parallelizing an application program. Specifically, provided is a method and system having multi-core control that may verify a number of available...
8640133 Equal duration and equal fetch operations sub-context switch interval based fetch operation scheduling utilizing fetch error rate based logic for switching between plurality of sorting algorithms  
Fetch operations are assigned to different threads in a multithreaded environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis...
8635620 Hardware device for processing the tasks of an algorithm in parallel  
A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary...
8631160 Development of parallel/distributed applications  
One embodiment of the present invention provides a method for supporting the development of a parallel/distributed application, wherein the development process comprises a design phase, an...
8627045 Postponing processing of received commands of pre-determined type until amount of associated data received and aggregated exceeds threshold to save power  
A data processing device including a reception unit, an instruction unit and a storage unit. The reception unit receives instructions for processing at a processing execution device. The...
8624910 Register indexed sampler for texture opcodes  
One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value...
8621185 Processor load determination and speed control  
Apparatus having corresponding methods and non-transitory computer-readable media comprise a processor, wherein the processor is configured to count a number of iterations of an idle task loop...
8621186 Obfuscated hardware multi-threading  
Obfuscating a multi-threaded computer program is carried out using an instruction pipeline in a computer processor by streaming first instructions of a first thread of a multi-threaded computer...
8621184 Effective scheduling of producer-consumer processes in a multi-processor system  
A novel technique for improving throughput in a multi-core system in which data is processed according to a producer-consumer relationship by eliminating latencies caused by compulsory cache...
8615767 Using IR drop data for instruction thread direction  
A data processing system having a memory for storing instructions and several central processing units for executing instructions, each central processing unit including an adaptive power supply...
8615645 Controlling the selectively setting of operational parameters for an adapter  
An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters,...
8612729 Known good code for on-chip device management  
In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural...
8607031 Hardware device for processing the tasks of an algorithm in parallel  
A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary...
8607032 Diagnose instruction for serializing processing  
A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used...
8601242 Adaptive optimized compare-exchange operation  
A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange...
8601241 General purpose register cloning  
A clone set of General Purpose Registers (GPRs) is created to be used by a set of helper thread binaries, which is created from a set of main thread binaries. When the set of main thread binaries...
8595731 Low overhead dynamic thermal management in many-core cluster architecture  
A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread...
8595469 Diagnose instruction for serializing processing  
A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used...
8595470 DSP performing instruction analyzed m-bit processing of data stored in memory with truncation / extension via data exchange unit  
A digital signal processor includes an instruction analysis unit, a digital signal processor (DSP) core and a memory unit. The instruction analysis unit receives an instruction and determines the...
8589664 Program flow control  
A data processing apparatus includes a data engine 6 having an instruction decoder 18 for generating one or more control signals 24 for controlling processing circuitry 20 to perform data...
8589656 Queuing of conflicted remotely received transactions  
Queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the...
8589663 Technique to perform three-source operations  
A technique to perform three-source instructions. At least one embodiment of the invention relates to converting a three-source instruction into at least two instructions identifying no more than...
8589925 Techniques for switching threads within routines  
Various technologies and techniques are disclosed for switching threads within routines. A controller routine receives a request from an originating routine to execute a coroutine, and executes the...
8589734 Verifying correctness of processor transactions  
An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated...
8572624 Providing multiple quiesce state machines in a computing environment  
A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The...
8572588 Thread-local memory reference promotion for translating CUDA code for execution by a general purpose processor  
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit...
8572355 Support for non-local returns in parallel thread SIMD engine  
One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the...
8565811 Software-defined radio using multi-core processor  
A radio control board passes a plurality of digital samples between a memory of a computing device and a radio frequency (RF) transceiver coupled to a system bus of the computing device. Processing...
8566567 System to profile and optimize user software in a managed run-time environment  
Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture...
8560814 Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations  
Systems and methods for efficient execution of operations in a multi-threaded processor. Each thread may include a blocking instruction. A blocking instruction blocks other threads from utilizing...
8554856 Enforced unitasking in multitasking systems  
A computer system includes one or more devices that are capable of multitasking (performing at least two tasks in parallel or substantially in parallel). In response to detecting that one of the...
8555036 System and method for performing predicated selection of an output register  
A system includes a processor having an instruction register for storing an instruction having a predefined opcode, a predicate register for storing a predicate condition to select an output...
8555251 Signal processing apparatus with user-configurable circuit configuration  
A signal processing apparatus for performing signal processing including a plurality of steps in data units by software signal processing includes signal processing modules performing the steps, a...
8549185 Facilitating transport mode input/output operations between a channel subsystem and input/output devices  
A computer program product is provided for performing an input/output (I/O) processing operation at a host computer system. The computer program product is configured to perform: obtaining a...
8549258 Configurable processing apparatus and system thereof  
A configurable processing apparatus includes a plurality of processing units, at least an instruction synchronization control circuit, and at least a configuration memory. Each processing apparatus...
8544031 Use of modes for computer cluster management  
A system, method and computer program product for managing a plurality of applications in a computer cluster. Each application is able to run on a particular node in the cluster. In one embodiment,...
RE44494 Processor having execution core sections operating at different clock rates  
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations...