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7624255 Scheduling program instruction execution by using fence instructions  
A system and method controls the scheduling of program instructions included in a shader program for execution by a processing pipeline. One or more fence instructions may be inserted into the...
RE41012 Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor  
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the...
7617385 Method and apparatus for measuring pipeline stalls in a microprocessor  
A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a...
7617384 Structured programming control flow using a disable mask in a SIMD architecture  
One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A...
7613908 Selective hardware lock disabling  
Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a...
7613907 Embedded software camouflage against code reverse engineering  
Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will...
7610471 Data processor  
The data processor executes an instruction having a direction for write to a reference register of other instruction flow and an instruction having a direction for reference register invalidation....
7610470 Preventing register data flow hazards in an SST processor  
One embodiment of the present invention provides a system that prevents data hazards during simultaneous speculative threading. The system starts by executing instructions in an execute-ahead mode...
7606998 Store instruction ordering for multi-core processor  
A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by...
7606974 Automatic caching generation in network applications  
Automatic software controlled caching generations in network applications are described herein. In one embodiment, a candidate representing a plurality of instructions of a plurality of threads...
7603673 Method and system for reducing context switch times  
An apparatus for managing resource in a multithreaded system, and attempting to increase the speed in which task switching occurs by controlling when thread state is stored to memory. The apparatus...
7603543 Method, apparatus and program product for enhancing performance of an in-order processor with long stalls  
A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data...
7603542 Reconfigurable electric computer, semiconductor integrated circuit and control method, program generation method, and program for creating a logic circuit from an application program  
An application program is executed and is easily made reusable by dividing the application program into processing units, and by creating a logical circuit in the reconfigurable hardware by...
7603346 Integrated search engine devices having pipelined search and b-tree maintenance sub-engines therein  
A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory...
7600099 System and method for predictive early allocation of stores in a microprocessor  
A system and method for predictive early allocation of stores in a microprocessor is presented. During instruction dispatch, an instruction dispatch unit retrieves an instruction from an...
7594098 Processes and devices for compression and decompression of executable code by a microprocessor with RISC architecture and related system  
An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into...
7587581 Multiple-thread processor with in-pipeline, thread selectable storage  
A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal...
7587578 Processing only those that need processing among divided portions of input data and binding with unprocessed portions while allowing reconfiguration of processing logic device for next input  
Provided is a reconfigurable processor or apparatus capable of changing a logic without any loss of input data and without any deterioration of data computing processing performance, which is...
7584344 Instruction for conditionally yielding to a ready thread based on priority criteria  
An integrated circuit ( 10 ) has a conditional yield instruction ( 305 ) which may be used to conditionally yield execution of a currently active thread based on priority and status of other...
7583262 Optimization of time-critical software components for real-time interactive applications  
A method for optimizing the performance of a time-critical computation component for a real-time interactive application includes the use of an algorithm having a precise logical thread and at...
7581091 System and method for extracting fields from packets having fields spread over more than one register  
Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register...
7581086 Digital signal processor  
A digital signal processor is provided, comprising at least one cluster. The cluster may comprise at least two function units each conducting different instruction types, at least two private...
7581085 Fast stub and frame technology for virtual machine optimization  
A method and system for handling of potential unsafe instructions and/or for handling transfers of control in a Virtual Machine, that includes generating a frame composed of pages of analyzed code...
7580914 Method and apparatus to improve execution of a stored program  
In one embodiment, the invention provides a method comprising determining metadata encoded in instructions of a stored program; and executing the stored program based on the metadata.
7577952 Common state sequences in a finite state machine  
A state machine may have a sequence that is called by multiple threads within the state machine. Prior to calling the sequence, an address specific to the current state is stored in an address...
7577826 Stall prediction thread management  
Thread switching prevents pipeline stalls when executing multiple threads. An analysis of a first thread identifies instructions capable of causing pipeline stalls. If pipeline stalls from the...
7571303 Reconfigurable integrated circuit  
A reconfigurable integrated circuit is provided wherein the available hardware resources can be optimised for a particular application. Dynamically reconfiguring (in both real-time and non...
7568087 Partial load/store forward prediction  
In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load...
7568086 Cache for instruction set architecture using indexes to achieve compression  
A method for compressing a set of instructions in an adaptive computing machine includes identifying frequently executed instructions, inserting an explicit caching instruction associating the...
7565514 Parallel condition code generation for SIMD operations  
A processing system and method performs data processing operations in response to a single data processing instruction. At least two registers store data. First control circuitry compares data in...
7565512 Method, system and apparatus for generation of global branch history  
Systems, methods and apparatuses for the generation of a global history are disclosed. Embodiments of the present invention may provide logic operable to generate a global history and a global...
7558946 Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach  
In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of...
7552316 Method and apparatus for compressing instructions to have consecutively addressed operands and for corresponding decompression in a computer system  
The apparatus and methods improve performance in a computer system by compressing a plurality of instructions having the same function with consecutively addressed operands and decompressing the...
7552247 Increased computer peripheral throughput by using data available withholding  
A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and...
7546441 Coprocessor interface controller  
A controller interface between a processor and a coprocessor is described. The controller is coupled to the processor to provide a processor interface for operating at a first frequency, where the...
7543293 Privelege level changing for virtual memory mapping  
Described is a system and method whereby processes may have multiple memory maps associated therewith to provide curtained memory and overcome other memory-related problems. Multiple maps are used...
7540026 No-execute processor feature global disabling prevention system and method  
A method includes stalling execution of a model specific register write function to write to a model specific register of a processor having a no-execute processor feature enabled, determining that...
7539851 Using register readiness to facilitate value prediction  
One embodiment of the present invention provides a system for using register readiness to facilitate value prediction. The system starts by loading a previously computed result for a function to a...
7536535 Self-timed processor  
Systems and methods for executing program instructions in a data processor at a variable rate. In one embodiment, a processor is configured to examine received instructions, identify an execution...
7533238 Method for limiting the size of a local storage of a processor  
A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a...
7529918 System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor  
A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a...
7529914 Method and apparatus for speculative execution of uncontended lock instructions  
A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will...
7529909 Security verified reconfiguration of execution datapath in extensible microcomputer  
Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines...
7523297 Shadow scan decoder  
Methods and circuitry for processing a shadow scan instruction in a multi-threaded microprocessing environment include a bit sequence having a thread identifier, core identifiers and a shadow scan...
7523230 Device and method for maximizing performance on a memory interface with a variable number of channels  
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
7519696 Method and apparatus for dynamically modifying a computer system configuration  
One embodiment is directed to a method and apparatus for modifying a configuration of a computer system including a host computer and at least one computer system resource accessible to at least...
7512930 Program object read barrier  
A method and apparatus for a read barrier mechanism are described. According to an embodiment, a method comprises receiving an access request for a program object; performing a combined check for a...
7512771 Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit  
Mapping circuitry ( 40 ) comprises a first candidate output value producing unit ( 42 ) which produces a first candidate output value (Cl) that differs by a first offset value (x) from a received...
7512498 Streaming processing of biological sequence matching  
A data system is provided for biological sequence matching. The system includes a system memory, a cache controller coupled to the system memory, a first cache coupled to the cache controller to...
7509399 Programmable communication interface  
A device comprises a programmable communication interface and a processor. The programmable communication interface communicates data via a set of signals. The processor configures the programmable...
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