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7512498 |
Streaming processing of biological sequence matching
A data system is provided for biological sequence matching. The system includes a system memory, a cache controller coupled to the system memory, a first cache coupled to the cache controller to...
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7512930 |
Program object read barrier
A method and apparatus for a read barrier mechanism are described. According to an embodiment, a method comprises receiving an access request for a program object; performing a combined check for a...
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7509399 |
Programmable communication interface
A device comprises a programmable communication interface and a processor. The programmable communication interface communicates data via a set of signals. The processor configures the programmable...
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7502916 |
Processing arrangement, memory card device and method for operating and manufacturing a processing arrangement
A processing arrangement ( 1 ) includes a processing unit ( 3 ) adapted to execute a predetermined set of processing instructions received from an instruction input ( 12 ). The set of processing...
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7503048 |
Scheduling synchronization of programs running as streams on multiple processors
Systems and methods for scheduling program units that are part of a process executed within an operating system are disclosed. Additionally, at least one thread is started within the operating...
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7496921 |
Processing block with integrated light weight multi-threading support
A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various...
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7493477 |
Method and apparatus for disabling a processor core based on a number of executions of an application exceeding a threshold
A system includes a multi-core processor including a first processor core and a second processor core, and a core manager. The core manager is to receive data during an execution of an application...
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7493447 |
System and method for caching sequential programs
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
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7493476 |
Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence
A processor is provided that includes decode logic coupled to an instruction cache and a micro-sequence vector table including entries for each bytecode in an instruction set of the processor. The...
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7490210 |
System and method for processor with predictive memory retrieval assist
A system and method for memory control. The system includes a hard-IP memory controller, a soft-IP frequency conversion system, and an interface system. The soft-IP frequency conversion system is...
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7487505 |
Multithreaded microprocessor with register allocation based on number of active threads
A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.
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7484079 |
Pipeline stage initialization via task frame accessed by a memory pointer propagated among the pipeline stages
An embodiment of the present invention includes a pipeline comprising a plurality of stages and a pipeline timing controller controlling a plurality of predetermined delays, wherein, when one of...
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7480771 |
Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged
We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated,...
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7480797 |
Method and system for preventing current-privilege-level-information leaks to non-privileged code
Various embodiments of the present invention introduce privilege-level mapping into a computer architecture not initially designed for supporting virtualization. Privilege-level mapping can, with...
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7480754 |
Assignment of queue execution modes using tag values
The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host....
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7475228 |
Ensuring progress in a system that supports execution of obstruction-free operations
One embodiment of the present invention provides a system that ensures that progress is made in an environment that supports execution of obstruction-free operations. During execution, when a...
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7464254 |
Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data
A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a...
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7461239 |
Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines
Mechanisms for handling data cache misses out-of-order for asynchronous pipelines are provided. The mechanisms associate load tag (LTAG) identifiers with the load instructions and uses them to...
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7461241 |
Concurrent physical processor reassignment method
Reassignment of a physical processor backing a logical processor is performed concurrently to the operation of the processor. The operating state of one physical processor is loaded on another...
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7461240 |
Command execution controlling apparatus, command execution instructing apparatus and command execution controlling method
The issuance timing of commands received from and transmitted to among a plurality of processing units is controlled efficiently. An execution command storage unit 222 stores execution commands,...
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7454596 |
Method and apparatus for partitioned pipelined fetching of multiple execution threads
Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a...
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7451296 |
Method and apparatus for pausing execution in a processor or the like
A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET...
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7444498 |
Load lookahead prefetch for microprocessors
The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the...
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7441105 |
Reducing multiplexer circuitry for operand select logic associated with a processor
Methods and apparatus are provided for reducing the amount of resources allocated for handling multiplexing in a processor. Characteristics associated with processing blocks are analyzed. Operand...
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7441239 |
Computer program product method and computer in role-based application systems
A role-based computer system has a first processor with a computer program ( 100 ) and has further processors with application systems (Sy 1 , Sy 2 , Sy 3 ) and application services (Se). The...
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7441245 |
Phasing for a multi-threaded network processor
A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units...
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7437533 |
Quantum information processing device and method
Quantum information processing device includes resonator incorporating material containing physical systems, each of physical systems having at least four energy states, transition between two...
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7437724 |
Registers for data transfers
A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a...
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7433981 |
System and method for using co-processor hardware to accelerate highly repetitive actions
An architecture is described, wherein an operation unit, such as an arithmetic unit, is used for performing a variety of repetitive tasks. The present invention includes embodiments and related...
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7430655 |
Method and software for multithreaded processor with partitioned operations
A system and software for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads,...
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7430737 |
Processor and method for supporting compiler directed multithreading management
In one embodiment, a processor includes an execution unit configured to execute one or more threads and a detection unit coupled to detect whether a given thread includes an identifier. The...
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7421567 |
Using a modified value GPR to enhance lookahead prefetch
The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction...
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7421568 |
Power saving methods and apparatus to selectively enable cache bits based on known processor state
A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes...
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7415383 |
Compiling method, apparatus, and program
Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a...
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7415598 |
Message synchronization in network processors
Message synchronization in network processors includes passing data from a producer processor to an inter-processor ring structure, while setting a bit in a register and reading the register by a...
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7412589 |
Method to detect a stalled instruction stream and serialize micro-operation execution
A computer implemented method, apparatus, and computer usable program code for ensuring forward progress of instructions in a pipeline of a processor. Instructions are received in the pipeline....
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7406573 |
Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements
A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor...
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7401176 |
Method and system for fast access to stack memory
Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit...
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7395538 |
Scalable packet processing systems and methods
A data processing architecture includes multiple processors connected in series between a load balancer and reorder logic. The load balancer is configured to receive data and distribute the data...
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7389391 |
Memory disposition methods and systems
A memory disposition system, comprising a first memory device and a second memory device. First and second memory devices are provided to a system, such as an embedded system. The first and the...
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7389404 |
Apparatus and method for matrix data processing
A matrix data processor is implemented wherein data elements are stored in physical registers and mapped to logical registers. After being stored in the logical registers, the data elements are...
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7386636 |
System and method for communicating command parameters between a processor and a memory flow controller
A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary...
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7383427 |
Multi-scalar extension for SIMD instruction set processors
A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The...
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7383426 |
Processor employing loadable configuration parameters to reduce or eliminate setup and pipeline delays in a pipeline system
A deep-pipeline system substantially reduces the overhead of setup delays and pipeline delays by dynamically controlling access of a plurality of configuration register sets by both a host central...
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7376844 |
Countermeasure method for a microcontroller based on a pipeline architecture
A countermeasure method for a microcontroller that executes sequences of instructions. The instructions are executed according to a pipeline method. At least one waiting time is randomly introduced...
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7373487 |
Controller with fail-safe function
A master CPU and a slave CPU for processing data supplied from a detector unit, and a timer cleared by a clear signal supplied every predetermined time period from the master CPU when the operation...
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7370179 |
Microprocessor
The invention relates to a microprocessor having a plurality of components which are selected from registers ( 14,16 ), arithmetic logic units ( 30,32 ), memory ( 36,38 ), input/output circuits and...
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7370159 |
Microprocessor having an extended addressable space
A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space....
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7366881 |
Method and apparatus for staggering execution of an instruction
A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro...
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7363625 |
Method for changing a thread priority in a simultaneous multithread processor
An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in...
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