|
Match
|
Document |
Document Title |
|
|
8180998 |
System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations
A system for performing data-parallel operations and task-parallel operations. A first switch fabric node (SFN) includes first and second lane processing engines (LPEs). The first LPE includes a...
|
|
|
8176290 |
Memory controller
A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an...
|
|
|
8171263 |
Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions
A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing...
|
|
|
8171464 |
Efficient code generation using loop peeling for SIMD loop code with multile misaligned statements
An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if...
|
|
|
8161267 |
Methods and apparatus for scalable array processor interrupt detection and response
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
|
|
|
8161271 |
Store misaligned vector with permute
Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By...
|
|
|
8161280 |
Launching a secure kernel in a multiprocessor system
In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and...
|
|
|
8146150 |
Security management in multi-node, multi-processor platforms
Multi-node and multi-processor security management is described in this application. Data may be secured in a TPM of any one of a plurality of nodes, each node including one or more processors. The...
|
|
|
8146092 |
System and method for selecting and executing an optimal load distribution processing in a storage system
A controller having a plurality of cores extracts, for each logical unit (LU), a pattern showing the relationship between a core having an LU ownership and a candidate core as an LU ownership...
|
|
|
8131981 |
SIMD processor performing fractional multiply operation with saturation history data processing to generate condition code flags
A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing...
|
|
|
8127112 |
SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream
A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input...
|
|
|
8122227 |
SIMD processor for performing data filtering and/or interpolation
A data processing circuit contains an instruction execution circuit that has an instruction set that comprises a SIMD instruction. The instruction execution circuit comprises a plurality of...
|
|
|
8112691 |
Method for efficient generation of a Fletcher checksum using a single SIMD pipeline
The generation of Fletcher/Alder partial checksums are transformed from a space that requires integer multiplications and additions to a space that requires only integer additions and shifts on a...
|
|
|
8112614 |
Parallel data processing systems and methods using cooperative thread arrays with unique thread identifiers as an input to compute an identifier of a location in a shared memory
Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an...
|
|
|
8108653 |
Processor architectures for enhanced computational capability and low latency
A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive...
|
|
|
8108846 |
Compiling scalar code for a single instruction multiple data (SIMD) execution engine
A mechanism is provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are...
|
|
|
8103854 |
Methods and apparatus for independent processor node operations in a SIMD array processor
A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread...
|
|
|
8099584 |
Methods for scalably exploiting parallelism in a parallel processing system
Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual...
|
|
|
8086830 |
Arithmetic processing apparatus
An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation...
|
|
|
8085264 |
Tile output using multiple queue output buffering in a raster stage
A method for multiple queue output buffering in a raster stage of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics...
|
|
|
8082419 |
Residual addition for video software techniques
According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a...
|
|
|
8078836 |
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands...
|
|
|
8074058 |
Providing extended precision in SIMD vector arithmetic operations
The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data...
|
|
|
8069334 |
Parallel histogram generation in SIMD processor by indexing LUTs with vector data element values
The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of...
|
|
|
8060725 |
Processor architecture with processing clusters providing vector and scalar data processing capability
A processor architecture for multimedia applications includes processor clusters providing vectorial data processing capability. Processing elements in the processor clusters process both data with...
|
|
|
8060724 |
Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
Executing a first memory access instruction with update by an N-bit processor includes accessing at least one source register of a plurality of registers, wherein the accessing includes accessing a...
|
|
|
8060726 |
SIMD microprocessor, image processing apparatus including same, and image processing method used therein
A SIMD microprocessor, which can be included in an image processing apparatus using an image processing method used therein, includes a global processor and multiple processor elements controlled...
|
|
|
8056069 |
Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization
A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains...
|
|
|
8041927 |
Processor apparatus and method of processing multiple data by single instructions
A processor (and method) of processing multiple data by a single instruction includes first and second register sets each of which includes a plurality of registers, and an arithmetic unit to...
|
|
|
8032735 |
Load/move duplicate instructions for a processor
A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion...
|
|
|
8028150 |
Runtime instruction decoding modification in a multi-processing array
A method and system for decoding and modifying processor instructions in runtime according to certain rules in order to separately control processing elements embedded within a multi-processor...
|
|
|
8024549 |
Two-dimensional processor array of processing elements
A data processor apparatus comprises a plurality of data receiving means each for receiving data from a data source; a computational element coupleable to each of said data receiving means for...
|
|
|
8024531 |
Information processing system and information processing method
An ascending ordered list without duplication is generated based on a value list divided and held by multiple memory modules. An information processing system has multiple PMMs (Processor Memory...
|
|
|
8024550 |
SIMD processor with each processing element receiving buffered control signal from clocked register positioned in the middle of the group
Disclosed is an SIMD-type microprocessor comprising a processor element group, plural processor elements with an operation part and a register file being arranged therein and a processor element...
|
|
|
8010953 |
Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine
Performing scalar operations using a SIMD data parallel execution unit is provided. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that...
|
|
|
8001506 |
SIMD image forming apparatus for minimizing wiring distance between registers and processing devices
A disclosed image processing apparatus includes a SIMD microprocessor in which multiple processor elements are arranged in one dimension, each of the processor elements including multiple access...
|
|
|
7996572 |
Multi-node chipset lock flow with peer-to-peer non-posted I/O requests
Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment...
|
|
|
7966475 |
Parallel data processing apparatus
A data processor comprises a plurality of processing elements arranged for parallel processing of data, and a controller for controlling the plurality of processing elements. The controller is...
|
|
|
7962718 |
Methods for performing extended table lookups using SIMD vector permutation instructions that support out-of-range index values
A permutation instruction generates vector elements for a destination register using identified source and destination registers. A plurality of partial table lookups corresponding to an extended...
|
|
|
7958332 |
Parallel data processing apparatus
A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction...
|
|
|
7941570 |
Bi-directional data transfer within a single I/O operation
An article of manufacture, apparatus, and a method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit....
|
|
|
7937567 |
Methods for scalably exploiting parallelism in a parallel processing system
Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual...
|
|
|
7925861 |
Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution
A data processor comprises a plurality of processing elements arranged in a first plurality of single instruction multiple data (SIMD) processing arrays, and comprises a second plurality of...
|
|
|
7917727 |
Data processing architectures for packet handling using a SIMD array
An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The...
|
|
|
7916864 |
Graphics processing unit used for cryptographic processing
A graphics processing unit is programmed to carry out cryptographic processing so that fast, effective cryptographic processing solutions can be provided without incurring additional hardware...
|
|
|
7908461 |
Cellular engine for a data processing system
A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of...
|
|
|
7904905 |
System and method for efficiently executing single program multiple data (SPMD) programs
A system and method is disclosed for efficiently executing single program multiple data (SPMD) programs in a microprocessor. A micro single instruction multiple data (SIMD) unit is located within...
|
|
|
7903810 |
Single instruction for data scrambling
A method and apparatus are disclosed for efficiently scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for scrambling one...
|
|
|
7900025 |
Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations
Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit...
|
|
|
7895412 |
Programmable arrayed processing engine architecture for a network switch
A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as...
|