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7599489 |
Accelerating cryptographic hash computations
Provided is an apparatus and method for accelerating cryptographic hash computations. For example, in a cryptographic hash computation such as SHA-1, multiple execution units in a processor can...
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7596679 |
Interconnections in SIMD processor architectures
A single instruction multiple data (SIMD) processor ( 1 ) comprises a processing element array ( 10 ) including a plurality of processing elements (PEO . . . PEN), and a memory array ( 14 )...
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7594095 |
Multithreaded SIMD parallel processor with launching of groups of threads
In a multithreaded processing core, groups of threads are launched in parallel for single-instruction, multiple-data (SIMD) execution by a set of parallel processing engines. Thread-specific input...
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7584342 |
Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue
Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an...
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7580412 |
System and method for generating header error control byte for Asynchronous Transfer Mode cell
In an Asynchronous Transfer Mode cell, a method and apparatus are disclosed for producing a cell header having bytes with bits in reverse order. Address and control data bytes are received, and a...
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7568085 |
Scalable FPGA fabric architecture with protocol converting bus interface and reconfigurable communication path to SIMD processing elements
A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW)...
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7565514 |
Parallel condition code generation for SIMD operations
A processing system and method performs data processing operations in response to a single data processing instruction. At least two registers store data. First control circuitry compares data in...
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7565287 |
Methods and apparatus for efficient vocoder implementations
Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing...
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7546443 |
Providing extended precision in SIMD vector arithmetic operations
The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data...
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7539846 |
SIMD processor with a subroutine control unit
The invention relates to a method and an apparatus for controlling a digital signal processor having a number of arithmetic units ( 1 a, 1 b ) which process a program ( 8 ). A control unit ( 5 )...
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7536532 |
Merge operations of data arrays based on SIMD instructions
A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with...
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7516299 |
Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions
A method for transferring data from a general purpose register (GPR) to a vector register (VR), the method including vectorially combining data in the VR from the GPR, by executing instructions of...
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7509602 |
Compact processor element for a scalable digital logic verification and emulation system
A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages.
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7506136 |
Parallel data processing apparatus
A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a...
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7506135 |
Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements
The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of...
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7496673 |
SIMD-RISC microprocessor architecture
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and...
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7490190 |
Method and system for local memory addressing in single instruction, multiple data computer system
A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”)...
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7484076 |
Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P)
Methods, apparatuses, and systems are presented for performing instructions using multiple execution units in a graphics processing unit involving issuing an instruction for P executions of the...
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7480785 |
Parallel processing device and parallel processing method
A row decoding circuit ( 171 ) outputs a select signal to a row set in a row range setting unit ( 172 ) to select a select signal line ( 103 ), processing results from processing circuits ( 102 )...
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7467288 |
Vector register file with arbitrary vector addressing
A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a...
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7467286 |
Executing partial-width packed data instructions
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the...
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7460989 |
Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language
A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs...
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7457941 |
Vector processing system
A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the...
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7454749 |
Scalable parallel processing on shared memory computers
A virtual parallel computer is created within a programming environment comprising both shared memory and distributed memory architectures. At run time, the virtual architecture is mapped to a...
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7454594 |
Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements
A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and...
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7453882 |
Apparatus and method for asynchronously controlling data transfers across long wires
One embodiment of the present invention provides a system that asynchronously controls the sending of data items from a sender to a receiver. The system includes a data path between the sender and...
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7451294 |
Apparatus and method for two micro-operation flow using source override
A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single...
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7447873 |
Multithreaded SIMD parallel processor with loading of groups of threads
In a multithreaded processing core, groups of threads are executed using single instruction, multiple data (SIMD) parallelism by a set of parallel processing engines. Input data defining objects to...
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7444496 |
Apparatus, system, and method for determining the consistency of a database
An apparatus, system, and method are disclosed for determining the consistency of a database including indirect reference to data elements. There is provided an apparatus for determining...
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7441099 |
Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit
Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to...
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7441098 |
Conditional execution of instructions in a computer
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation...
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7412587 |
Parallel operation processor utilizing SIMD data transfers
A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit...
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7401204 |
Parallel Processor efficiently executing variable instruction word
A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information....
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7395531 |
Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements
A system and method is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized...
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7392368 |
Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements
Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate...
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7392329 |
System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices
In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The...
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7383421 |
Cellular engine for a data processing system
A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of...
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7376812 |
Vector co-processor for configurable and extensible processor architecture
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one...
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7373488 |
Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values
A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a...
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7367026 |
Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization
A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains...
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7363478 |
Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index
A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data...
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7363472 |
Memory access consolidation for SIMD processing elements having access indicators
A data processing apparatus includes a SIMD (Single Instruction Multiple Data) array ( 10 ) of processing elements. The processing elements are operably divided into a plurality of processing...
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7360063 |
Method for SIMD-oriented management of register maps for map-based indirect register-file access
A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each...
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7350057 |
Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction
Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for...
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7328371 |
Core redundancy in a chip multiprocessor for highly reliable systems
In one embodiment, a node comprises a plurality of processor cores and a node controller coupled to the processor cores. The node controller is configured to route communications from the processor...
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7315932 |
Data processing system having instruction specifiers for SIMD register operands and method thereof
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of...
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7313788 |
Vectorization in a SIMdD DSP architecture
A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access...
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7313646 |
Interfacing of functional modules in an on-chip system
An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication...
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7308559 |
Digital signal processor with cascaded SIMD organization
A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD...
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7296120 |
Mechanism that provides efficient multi-word load atomicity
Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the...
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