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8996845 Vector compare-and-exchange operation  
A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of...
8959319 Executing first instructions for smaller set of SIMD threads diverging upon conditional branch instruction  
Embodiments of the present invention provide systems, methods, and computer program products for improving divergent conditional branches in code being executed by a processor. For example, in an...
8954943 Analyze and reduce number of data reordering operations in SIMD code  
A method for analyzing data reordering operations in Single Issue Multiple Data source code and generating executable code therefrom is provided. Input is received. One or more data reordering...
8918553 Multithreaded programmable direct memory access engine  
A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated...
8914613 Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits  
In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands...
8898432 Folded SIMD array organized in groups (PEGs) of respective array segments, control signal distribution logic, and local memory  
Systems and methods for folding a single instruction multiple data (SIMD) array include a newly defined processing element group (PEG) that allows interconnection of PEGs by abutment without...
8892781 Bi-directional data transfer within a single I/O operation  
A computer program product, apparatus, and a method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit....
8862827 Efficient multi-level software cache using SIMD vector permute functionality  
A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used...
8856494 SIMD processor for performing data filtering and/or interpolation  
Data processing circuit containing an instruction execution circuit having an instruction set comprising a SIMD instruction. The instruction execution circuit comprises arithmetic circuits,...
8838946 Packing lower half bits of signed data elements in two source registers in a destination register with saturation  
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data...
8832417 Program flow control for multiple divergent SIMD threads using a minimum resume counter  
This disclosure describes techniques for handling divergent thread conditions in a multi-threaded processing system. In some examples, a control flow unit may obtain a control flow instruction...
8825987 Instruction and logic for processing text strings  
Methods, apparatus, and instructions for performing string comparison operations. An apparatus may include execution resources to execute a first instruction. In response to the first instruction,...
8819394 Instruction and logic for processing text strings  
Methods, apparatus, and instructions for performing string comparison operations. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the...
8775147 Algorithm and architecture for multi-argument associative operations that minimizes the number of components using a latency of the components  
An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for...
8769244 SIMD parallel computer system, SIMD parallel computing method, and control program  
Uniforming of the processing load is efficiently realized. Each processing element configuring an SIMD parallel computer system includes a data storage module that stores data processed or...
8762691 Memory access consolidation for SIMD processing elements using transaction identifiers  
A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive...
8756270 Collective acceleration unit tree structure  
A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an...
8751655 Collective acceleration unit tree structure  
A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an...
8745358 Processor to execute shift right merge instructions  
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data...
8732437 Low-overhead misalignment and reformatting support for SIMD  
Systems and methods for performing single instruction multiple data (SIMD) operations on a data set. The methods may include examining a structure of the data set to determine what reorganization...
8725990 Configurable SIMD engine with high, low and mixed precision modes  
A configurable SIMD engine in a video processor for executing video processing operations. The engine includes a SIMD component having a plurality of inputs for receiving input data and a...
8726252 Management of conditional branches within a data parallel system  
A compiler of a single instruction multiple data (SIMD) information handling system (IHS) identifies “if-then-else” statements that offer opportunity for conditional branch conversion. The SIMD...
8713286 Register files for a digital signal processor operating in an interleaved multi-threaded environment  
A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one...
8700884 Single-instruction multiple-data vector permutation instruction and method for performing table lookups for in-range index values and determining constant values for out-of-range index values  
A processor in a data processing system executes a permutation instruction which identifies a first source register, at least one other source register, and a destination register. The first...
8688959 Method and apparatus for shuffling data  
Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L...
8688958 System for data collection from processing elements in a SIMD processor  
A processor has a plurality of PEs (processing elements) that operate in parallel based on operation commands and an information collection unit that collects the data of the plurality of PEs,...
8688957 Mechanism for conflict detection using SIMD  
A system and method are configured to detect conflicts when converting scalar processes to parallel processes (“SIMDifying”). Conflicts may be detected for an unordered single index, an ordered...
8661225 Data processing apparatus and method for handling vector instructions  
A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data...
8656376 Compiler for providing intrinsic supports for VLIW PAC processors with distributed register files and method thereof  
A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on...
8638805 Packet draining from a scheduling hierarchy in a traffic manager of a network processor  
Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules...
8639914 Packing signed word elements from two source registers to saturated signed byte elements in destination register  
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data...
8635432 SIMD processor array system and data transfer method thereof  
There is provided an SIMD processor array system in which data can be efficiently transferred between processor elements located at different distances. The SIMD processor array system includes a...
8612732 Retargetting an application program for execution by a general purpose processor  
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit...
8612507 Computing device, calculating method, and program product  
A computing device includes: a deciding unit which, in computation of values of nodes on a lattice in a direction where a value of m representing a horizontal axis coordinate of the lattice...
8605099 Partition-free multi-socket memory system architecture  
A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing...
8601246 Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register  
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data...
8595467 Floating point collect and operate  
Mechanisms are provided for performing a floating point collect and operate for a summation across a vector for a dot product operation. A routing network placed before the single instruction...
8587568 Integrated circuit device, electronic apparatus and method for manufacturing of electronic apparatus  
An integrated circuit device includes a host I/F, an information register, and a control section. The information register stores wave selection information for selecting waveform information...
8578387 Dynamic load balancing of instructions for execution by heterogeneous processing engines  
An embodiment of a computing system is configured to process data using a multithreaded SIMD architecture that includes heterogeneous processing engines to execute a program. The program is...
8572355 Support for non-local returns in parallel thread SIMD engine  
One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the...
8560809 Residual addition for video software techniques  
According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending...
8539201 Transposing array data on SIMD multi-core processor architectures  
Systems, methods and articles of manufacture are disclosed for transposing array data on a SIMD multi-core processor architecture. A matrix in a SIMD format may be received. The matrix may...
8539202 Load/move duplicate instructions for a processor  
A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent...
8532288 Selectively isolating processor elements into subsets of processor elements  
A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks...
8521994 Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation  
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data...
8510536 Vector completion mask handling  
Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation...
8493979 Single instruction processing of network packets  
Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.
8495253 Bi-directional data transfer within a single I/O operation  
An article of manufacture, apparatus, and a method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit....
8478969 Performing a multiply-multiply-accumulate instruction  
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple...
8464025 Signal processing apparatus with signal control units and processor units operating based on different threads  
A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 203—0 to 203—3 access data at an...

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