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8176301 Millicode assist instructions for millicode store access exception checking  
Millicode store access checking instructions are provided via an operand access control register (OACR) including a test modifier indicator, which is communicatively coupled to an instruction unit...
8176354 Wave pipeline with selectively opaque register stages  
A selectively synchronous wave pipeline segment and an integrated circuit (IC) including the segment. The segment includes a normally opaque input stage and output stage and multiple internal...
8166320 Power aware software pipelining for hardware accelerators  
Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline,...
8151268 Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency  
A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads...
8117425 Multithread processor and method of synchronization operations among threads to be used in same  
The Thread Data Base 1 holds a thread identifier to uniquely identify a thread in the system. The Check means 3 lets, when no thread being a target exist in the same processor, a trap (TRAP) 10...
8099583 Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing  
A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the...
8099582 Tracking deallocated load instructions using a dependence matrix  
A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the...
8086826 Dependency tracking for enabling successive processor instructions to issue  
An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains...
8082421 Program instruction rearrangement methods in computer  
A program instruction rearrangement method calculates the dependency depth of each instruction of a program based on dependency between instructions, based on register access order, and rearranging...
8078846 Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated  
A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies...
8065505 Stall-free pipelined cache for statically scheduled and dispatched execution  
This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled...
8055884 Method and apparatus for augmenting a pipeline with a bubble-removal circuit  
One embodiment of the present invention provides a system for augmenting a pipeline with a bubble-removal circuit. During operation, the system generates a bubble-removal circuit which determines a...
8037287 Error recovery following speculative execution with an instruction processing pipeline  
An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a...
8037366 Issuing instructions in-order in an out-of-order processor using false dependencies  
A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes...
8028151 Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines  
A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a...
8019974 Pipeline processor with write control and validity flags for controlling write-back of execution result data stored in pipeline buffer register  
A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity...
8006072 Reducing data hazards in pipelined processors to provide high processor utilization  
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on...
7984268 Advanced processor scheduling in a multithreaded system  
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and...
7975130 Method and system for early instruction text based operand store compare reject avoidance  
A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an...
7962726 Recycling long multi-operand instructions  
A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit...
7962730 Replaying memory operation assigned a load/store buffer entry occupied by store operation processed beyond exception reporting stage and retired from scheduler  
In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store...
7958340 Monitoring software pipeline performance on a network on chip  
Software pipelining on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP bloc...
7949855 Scheduler in multi-threaded processor prioritizing instructions passing qualification rule  
A processor buffers asynchronous threads. Instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one computation operation...
7945765 Method and structure for asynchronous skip-ahead in synchronous pipelines  
An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one...
7934031 Reshuffled communications processes in pipelined asynchronous circuits  
An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data...
7917793 Apparatus providing locally adaptive retiming pipeline with swing structure  
The present invention uses a swing structure to avoid using a clock period at a non-efficient execution time. The execution time is precisely controlled to enhance a performance of a processor...
7900023 Technique to enable store forwarding during long latency instruction execution  
A technique to allow independent loads to be satisfied during high-latency instruction processing. Embodiments of the invention relate to a technique in which a storage structure is used to hold...
7890733 Processor memory system  
A data processor comprises a plurality of processing elements (PEs), with memory local to at least one of the processing elements, and a data packet-switched network interconnecting the processing...
7882337 Method and system for efficient tentative tracing of software in multiprocessors  
A method of tentative tracing execution events in a multiprocessor system. Each processor stores tentative events in a corresponding buffer. The processor sets pointers in an array to a head and...
7877580 Branch lookahead prefetch for microprocessors  
A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during...
7865702 Stall prediction thread management  
Thread switching prevents pipeline stalls when executing multiple threads. An analysis of a first thread identifies instructions capable of causing pipeline stalls. If pipeline stalls from the...
7861064 Method, system, and computer program product for selectively accelerating early instruction processing  
A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a...
7861066 Mechanism for predicting and suppressing instruction replay in a processor  
A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution...
7849290 Store queue architecture for a processor that supports speculative execution  
Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue...
7844799 Method and system for pipeline reduction  
A method and system for operating a high frequency out-of-order processor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so...
7836279 Method and system for supporting software pipelining using a shifting register queue  
A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable...
7831810 Communicating signals between semiconductor chips using round-robin-coupled micropipelines  
Embodiments of the present invention provide a system for transferring data between a receiver chip and a transmitter chip. The system includes a set of data path circuits in the transmitter chip...
7818544 Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition  
Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an...
7814300 Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access  
A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction...
7802077 Trace indexing via trace end addresses  
A new class traces for a processing engine, called “extended blocks,” possess an architecture that permits possible many entry points but only a single exit point. These extended blocks may be ind...
7788473 Prediction of data values read from memory by a microprocessor using the storage destination of a load operation  
Prediction of data values to be read from memory by a microprocessor for load operations. In one aspect, a method for predicting a data value that will result from a load operation to be executed...
7779236 Symbolic store-load bypass  
The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to,...
7774582 Result bypassing to override a data hazard within a superscalar processor  
A data processing system including multiple execution pipelines each having multiple execution stages E1, E2, E3 may have instructions issued together in parallel despite a data dependency...
7761691 Method for allocating registers using simulated annealing controlled instruction scheduling  
A method for scheduling instructions for clustered digital signal processors comprising a plurality of clusters, each cluster including at least two functional units and a first register file...
7748001 Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time  
Method, apparatus and system embodiments to assign priority to a thread when the thread is otherwise unable to proceed with instruction retirement. For at least one embodiment, the thread is one of...
7734899 Reducing data hazards in pipelined processors to provide high processor utilization  
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on...
7730289 Method for preloading data in a CPU pipeline  
A method for preloading data in a CPU pipeline is provided, which includes the following steps. When a hint instruction is executed, allocate and initiate an entry in a preload table. When a load...
7725745 Power aware software pipelining for hardware accelerators  
Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline,...
7725685 Intelligent SMT thread hang detect taking into account shared resource contention/blocking  
Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is...
7725684 Speculative instruction issue in a simultaneously multithreaded processor  
A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers...
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