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7624254 Segmented pipeline flushing for mispredicted branches  
A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed...
7620799 Using a modified value GPR to enhance lookahead prefetch  
Mechanisms to identify and speculatively execute future instructions during a stall condition are provided. In speculative mode, instruction operands may be invalid due to a number of reasons....
7594097 Microprocessor output ports and control of instructions provided therefrom  
A method and apparatus are provided for controlling instructions provided by a microprocessor output port to other execution units. A microprocessor pipeline of instructions is provided for each...
7594078 D-cache miss prediction and scheduling  
A method and apparatus for D-cache miss prediction and scheduling is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one...
7552318 Branch lookahead prefetch for microprocessors  
A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during...
7530072 Method to segregate suspicious threads in a hosted environment to prevent CPU resource exhaustion from hung threads  
A system and method for segregating suspicious threads in a hosted environment to prevent CPU resource exhaustion from hung threads are disclosed. An application server identify suspicious threads...
7529913 Late allocation of registers  
Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the...
7516306 Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies  
The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend...
7496921 Processing block with integrated light weight multi-threading support  
A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various...
7487337 Back-end renaming in a continual flow processor pipeline  
The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands. ...
7475227 Method of stalling one or more stages in an interlocked synchronous pipeline  
A method of operating an integrated circuit including a pipeline and a method of stalling stages in the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are...
7472259 Multi-cycle instructions  
In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall...
7469407 Method for resource balancing using dispatch flush in a simultaneous multithread processor  
The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared...
7464242 Method of load/store dependencies detection with dynamically changing address length  
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming...
7454600 Method and apparatus for assigning thread priority in a processor or the like  
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further...
7454598 Controlling out of order execution pipelines issue tagging  
A method and system of controlling out of order execution pipelines using issue tags is disclosed. The issue tags are used to dynamically calculate pipeline skew parameters that track the relative...
7447879 Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss  
A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at...
7444498 Load lookahead prefetch for microprocessors  
The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the...
7441245 Phasing for a multi-threaded network processor  
A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units...
7441101 Thread-aware instruction fetching in a multithreaded embedded processor  
The present invention provides a multithreaded processor, such as a network processor, that fetches instructions in a pipeline stage based on feedback signals from later stages. The multithreaded...
7437539 Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline  
An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an...
7434033 Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline  
Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an...
7421567 Using a modified value GPR to enhance lookahead prefetch  
The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction...
7421566 Implementing instruction set architectures with non-contiguous register file specifiers  
There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code...
7418625 Deadlock detection and recovery logic for flow control based data path design  
Certain embodiments of the invention may be found in a method and system for handling deadlock conditions in a data processing system. Aspects of the method may comprise identifying a potential...
7406588 Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer  
A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid...
7404067 Method and apparatus for efficient utilization for prescient instruction prefetch  
Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map...
7401211 Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor  
In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can...
7398358 Method and apparatus for high performance branching in pipelined microsystems  
A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions,...
7366877 Speculative instruction issue in a simultaneously multithreaded processor  
A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers...
7363474 Method and apparatus for suspending execution of a thread until a specified memory access occurs  
Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A...
7363468 Load address dependency mechanism system and method in a high frequency, low power processor system  
The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At...
7360064 Thread interleaving in a multithreaded embedded processor  
The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization...
7356675 Data processor  
A data processor having: an instruction fetch unit for acquiring an instruction; and an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction...
7346760 Data processing apparatus of high speed process using memory of low speed and low power consumption  
When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout...
7343476 Intelligent SMT thread hang detect taking into account shared resource contention/blocking  
Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is...
7337305 Method and pipeline architecture for processing multiple swap requests to reduce latency  
A system and method of processing multiple swap requests including receiving a first swap request in a pipeline and executing the first swap request. A second swap request is also received in the...
7328330 Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor  
A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and...
7318145 Random slip generator  
A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be...
7316021 Switching method in a multi-threaded processor  
A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an...
7313673 Fine grained multi-thread dispatch block mechanism  
The present invention provides a method, a computer program product, and an apparatus for blocking a thread at dispatch in a multi-thread processor for fine-grained control of thread performance....
7310741 Phase adjusted delay loop executed by determining a number of NOPs based on a modulus value  
In an embodiment of the invention, a method for a phase adjusted delay loop, includes: determining a requested delay value for a code path; and executing a delay loop in the code path in order to...
7308593 Interlocked synchronous pipeline clock gating  
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively,...
7293163 Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency  
One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during...
7290121 Method and data processor with reduced stalling due to operand dependencies  
A data processor ( 200 ) has a pipelined execution unit ( 120 ). Whether a first instruction is one of a class of instructions wherein as a result of execution of the first instruction the contents...
7281120 Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor  
A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the...
7274369 Digital image compositing using a programmable graphics processor  
Digital Image compositing using a programmable graphics processor is described. The programmable graphics processor supports high-precision data formats and can be programmed to complete a...
7266675 Processor including a register file and method for computing flush masks in a multi-threaded processing system  
A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to...
7266674 Programmable delayed dispatch in a multi-threaded pipeline  
Detecting a stall condition associated with processor instructions within one or more threads and generating a no-dispatch condition. The stall condition can be detected by hardware and/or software...
7260707 Variable length instruction pipeline  
A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed...
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