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7613908 |
Selective hardware lock disabling
Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a...
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7613906 |
Advanced load value check enhancement
Systems and methods for performing re-ordered computer instructions are disclosed. A computer processor loads a first value from a first memory address, and records both the first value and the...
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7613905 |
Partial register forwarding for CPUs with unequal delay functional units
A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a critical functional unit. Each critical...
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7590827 |
Processor and instruction control method having a storage of latest register for updating data of source operands, and instruction control
A latest register update buffer which stores latest register update data is allocated and prepared every general register for storing source data. A latest register update processing unit stores a...
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7587585 |
Flag management in processors enabled for speculative execution of micro-operation traces
Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single...
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7581083 |
Operation processing device, system and method having register-to-register addressing
As shown in FIG. 1, an operation-processing device of the present invention comprises a register array ( 11 ) having plural registers for holding an arbitrary value based on a write address Aw...
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7568089 |
Flag management in processors enabled for speculative execution of micro-operation traces
Managing speculative execution via groups of actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints...
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7543134 |
Apparatus and method for extending a microprocessor instruction set
An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an...
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7536432 |
Parallel merge/sort processing device, method, and program for sorting data strings
In the basic form of merge processing, that is sort processing, two sorted partial data string pairs are input, and one series of sorted data string is output as a whole. Conventionally, high...
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7529913 |
Late allocation of registers
Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the...
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7523296 |
System and method for handling exceptions and branch mispredictions in a superscalar microprocessor
An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system...
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7523295 |
Processor and method of grouping and executing dependent instructions in a packet
An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a...
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7519794 |
High performance architecture for a writeback stage
In one embodiment, the present invention includes an apparatus that has a plurality of buffers to store data resulting from operations of a processor pipeline, a pointer storage to store pointers,...
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7516305 |
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system...
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7516302 |
Efficient use of co-processor in platform independent instruction machine by controlling result transfer and translation and transfer timing of subsequent instruction based on instruction type for result forwarding
A data processing method for processing a sequence of platform independent instructions on a data processing apparatus comprising a CPU and at least one further processor is disclosed. The data...
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7506140 |
Return data selector employing barrel-incrementer-based round-robin apparatus
A return data selector is disclosed. A pipelined microprocessor includes N functional units that request to return data to the pipeline. In a given selection cycle, some of the functional units may...
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7500086 |
Start transactional execution (STE) instruction to support transactional program execution
One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally....
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7496916 |
Service and recovery using multi-flow redundant request processing
Methods, systems and articles of manufacture for performing multiple request processing. Redundant instances of executing entities service requests in a time-delayed fashion, relative to one...
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7496735 |
Method and apparatus for incremental commitment to architectural state in a microprocessor
Method and hardware apparatus are disclosed for reducing the rollback penalty on exceptions in a microprocessor executing traces of scheduled instructions. Speculative state is committed to the...
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7496721 |
Packet processor memory interface with late order binding
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between the...
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7493508 |
Information processing device, method, and program
This invention relates to an information processing apparatus as well as to an information processing method and a program for use therewith, the apparatus being arranged to prevent a drop in its...
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7487335 |
Method and apparatus for accessing registers during deferred execution
One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order....
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7487304 |
Packet processor memory interface with active packet list
A mechanism receives start and done commands containing packet identifiers or sequence numbers from a packet processing engine for packets for which processing is being started and for which...
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7484078 |
Pipelined asynchronous instruction processor having two write pipeline stages with control of write ordering from stages to maintain sequential program ordering
A data processing circuit contains a register file ( 17 ) with a write port and a pipeline of instruction processing stages ( 10 a - d ). A timing circuit ( 14 ) is arranged to time transfer of...
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7478379 |
Method for minimizing spill in code scheduled by a list scheduler
A technique of ordering machine instructions to reduce spill code. For each machine instruction that is ready for scheduling, an amount is determined by which the size of a committed set of machine...
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7478276 |
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system...
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7478226 |
Processing bypass directory tracking system and method
A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural...
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7478209 |
Packet processor memory interface with conflict detection and checkpoint repair
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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7475226 |
System for managing data dependency using bit field instruction destination vector identifying destination for execution results
A method of data processing includes fetching a sequence of instructions, assigning each instruction within the sequence a respective unique instruction tag, and associating a respective...
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7475225 |
Method and apparatus for microarchitecture partitioning of execution clusters
Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are...
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7475201 |
Packet processor memory interface with conditional delayed restart
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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7475200 |
Packet processor memory interface with write dependency list
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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7472260 |
Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion
In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store...
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7472258 |
Dynamically shared group completion table between multiple threads
An SMT system has a dynamically shared GCT. Performance for the SMT is improved by configuring the GCT to allow an instruction group from each thread to complete simultaneously. The GCT has a read...
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7464242 |
Method of load/store dependencies detection with dynamically changing address length
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming...
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7454598 |
Controlling out of order execution pipelines issue tagging
A method and system of controlling out of order execution pipelines using issue tags is disclosed. The issue tags are used to dynamically calculate pipeline skew parameters that track the relative...
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7454532 |
Stream data interface for processing system
Techniques are provided for processing data in real-time or near real-time using a processor. The processor passes the real-time input data directly to functional units via a bypass multiplexer...
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7444497 |
Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support
A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method...
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7426630 |
Arbitration of window swap operations
In one embodiment, a processor comprises a register file, register management logic coupled to the register file, and at least two sources of window swap operations coupled to the register...
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7424598 |
Data processor
The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A...
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7421567 |
Using a modified value GPR to enhance lookahead prefetch
The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction...
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7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers
There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code...
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7418578 |
Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction groups
A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution...
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7418577 |
Fail instruction to support transactional program execution
One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the...
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7415601 |
Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters
A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for...
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7415597 |
Processor with dependence mechanism to predict whether a load is dependent on older store
A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store...
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7395416 |
Computer processing system employing an instruction reorder buffer
A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of...
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7395415 |
Method and apparatus to provide a source operand for an instruction in a processor
A method and apparatus for providing a source operand for an instruction to be executed in a processor. Some embodiments may include a register file unit that has registers and a scheduler to...
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7386707 |
Processor and program execution method capable of efficient program execution
A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a...
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7380104 |
Method and apparatus for back to back issue of dependent instructions in an out of order issue queue
A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following...
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