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9015450 Apparatus utilizing efficient hardware implementation of shadow registers and method thereof  
Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming...
8990544 Method and apparatus for using a previous column pointer to read entries in an array of a processor  
A method and apparatus are described for using a previous column pointer to read a subset of entries of an array in a processor. The array may have a plurality of rows and columns of entries, and...
8972701 Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register  
A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural...
8972700 Microprocessor systems and methods for latency tolerance execution  
An instruction unit provides instructions for execution by a processor. A decode unit decodes instructions received from the instruction unit. Queues are coupled to receive instructions from the...
8966230 Dynamic selection of execution stage  
Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in...
8933953 Managing active thread dependencies in graphics processing  
A scoreboard for a video processor may keep track of only dispatched threads which have not yet completed execution. A first thread may itself snoop for execution of a second thread that must be...
8930679 Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instruction  
An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry...
8914617 Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register  
Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data....
8914615 Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format  
A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is...
8914616 Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed  
A data processing apparatus and method are provided. A processor performs data processing operations in response to data processing instructions which reference logical registers. A set of...
8799626 Prioritized assignment of sub-range registers of circularly addressable extended register file to loop variables in RISC processor  
A segmental allocation method of expanding RISC processor register includes the steps of a) setting an instruction format of the RISC processor, the destination register field being set having 6...
8725989 Performing function calls using single instruction multiple data (SIMD) registers  
In one embodiment, a processor can perform a function call from a main program to a function that is to operate on at least one vector-type operand, in which only scalar values are passed to the...
8683180 Intermediate register mapper  
A method, processor, and computer program product employing an intermediate register mapper within a register renaming mechanism. A logical register lookup determines whether a hit to a logical...
8661230 Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions  
A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from...
8661228 Multi-level register file supporting multiple threads  
A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a...
8631223 Register file supporting transactional processing  
A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register...
8612728 Reducing data hazards in pipelined processors to provide high processor utilization  
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on...
8601177 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8583901 Register renaming system using multi-bank physical register mapping table and method thereof  
Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to...
8583900 Register renaming table recovery method and system for use in a processor  
A register renaming table recovery method for use in a processor includes the following steps. Firstly, a flushing operation is performed on a renaming-history table according to a flushed ID....
8578136 Apparatus and method for mapping architectural registers to physical registers  
An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical...
8544019 Thread queueing method and apparatus  
In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include...
8528000 Execution environment for data transformation applications  
The execution environment provides for scalability where components will execute in parallel and exploit various patterns of parallelism. Dataflow applications are represented by reusable dataflow...
8521982 Load request scheduling in a cache hierarchy  
A system and method for tracking core load requests and providing arbitration and ordering of requests. When a core interface unit (CIU) receives a load operation from the processor core, a new...
8464029 Out-of-order execution microprocessor with reduced store collision load replay reduction  
An out-of-order execution microprocessor for reducing load instruction replay likelihood due to store collisions. A register alias table (RAT) is coupled to first and second queues of entries and...
8386754 Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism  
An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register...
8370581 System and method for dynamic data prefetching  
According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination...
8364936 Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies  
In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency...
8346760 Method and apparatus to improve execution of a stored program  
In one embodiment, the invention provides a method comprising determining metadata encoded in instructions of a stored program; and executing the stored program based on the metadata.
8347068 Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor  
A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread...
8335912 Logical map table for detecting dependency conditions between instructions having varying width operand values  
Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used...
RE43825 System and method for data forwarding in a programmable multiple network processor environment  
A system and method forward data between processing elements. A first processing element includes an address register that stores a first memory address. A forwarding storage element is coupled to...
8271766 Intentionally delaying execution of a copy instruction to achieve simultaneous execution with a subsequent, non-adjacent write instruction  
An information processing device including registers (105) for holding data and an operation device (102) for executing arithmetic and logic operations on input/output data held in the register....
8255671 Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies  
In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency...
8250346 Register renaming of a partially updated data granule  
A processor 2 supporting register renaming has a rename table 20 in which the flag register has multiple tag values associated therewith. These tag values indicate which virtual register...
8250345 Structure for multi-threaded processing  
A design structure embodied in a machine readable storage medium designing, manufacturing, and/or testing a design that includes a multi-threaded processor that executes an instruction of a...
8245016 Multi-threaded processing  
A system includes a multi-threaded processor that executes an instruction of a process of an executing program. The multi-threaded processor includes at least a first and a second thread. First...
8239660 Processor with automatic scheduling of operations  
A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined...
8225012 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8225076 Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processor  
A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers...
8179896 Network processors and pipeline optimization methods  
A network processor of an embodiment includes a packet classification engine, a processing pipeline, and a controller. The packet classification engine allows for classifying each of a plurality...
8179540 Image forming apparatus and management system utilizing counter and job log information for usage tracking  
An image forming apparatus is provided that holds counter information obtained by integrating a consumption of a consumable that depends on usage of service provided by the image forming...
8171264 Control sub-unit and control main unit  
A sub-unit judges whether an instruction received from an external unit is executable. If the instruction is judged to be executable, the sub-unit executes it. If, on the other hand, the...
8151097 Multi-threaded system with branch  
When two threads (strands), for example, are executed in parallel in a processor in a simultaneous multi-thread (SMT) system, entries of a branch reservation station of an instruction control...
8135942 System and method for double-issue instructions using a dependency matrix and a side issue queue  
A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and...
8127083 Eliminating silent store invalidation propagation in shared memory cache coherency protocols  
A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A...
8127116 Dependency matrix with reduced area and power consumption  
A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first...
8122239 Method and apparatus for initializing a system configured in a programmable logic device  
Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with...
8082421 Program instruction rearrangement methods in computer  
A program instruction rearrangement method calculates the dependency depth of each instruction of a program based on dependency between instructions, based on register access order, and...
8078844 System, method, and computer program product for removing a register of a processor from an active state  
A system, method, and computer program product are provided for removing a register of a processor from an active state. In operation, an aspect of a portion of a processor capable of...