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7613905 |
Partial register forwarding for CPUs with unequal delay functional units
A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a critical functional unit. Each critical...
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7590827 |
Processor and instruction control method having a storage of latest register for updating data of source operands, and instruction control
A latest register update buffer which stores latest register update data is allocated and prepared every general register for storing source data. A latest register update processing unit stores a...
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7587532 |
Full/selector output from one of plural flag generation count outputs
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high...
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7577825 |
Method for data validity tracking to determine fast or slow mode processing at a reservation station
Devices, systems, and methods may perform micro-operation processing with data validity tracking to determine fast or slow mode processing at a reservation station. A method includes determining...
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7571302 |
Dynamic data dependence tracking and its application to branch prediction
A data dependence table in RAM relates physical register addresses to instructions such that for each instruction, the registers on whose data the instruction depends are identified. The table is...
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7565511 |
Working register file entries with instruction based lifetime
A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register...
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7558945 |
System and method for register renaming
A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the...
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7543109 |
System and method for caching data in a blade server complex
A method for caching data in a blade computing complex includes providing a storage blade that includes a disk operative to store pages of data and a cache memory operative to store at least one of...
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7539850 |
Enhanced virtual renaming scheme and deadlock prevention therefor
In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to...
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7516305 |
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system...
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7508396 |
Register-collecting mechanism, method for performing the same and pixel processing system employing the same
A pixel processing system includes a register-collecting mechanism and a pixel shader. The register-collecting mechanism corrects a first program to a second program. The first program requires a...
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7506139 |
Method and apparatus for register renaming using multiple physical register files and avoiding associative search
A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions...
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7496735 |
Method and apparatus for incremental commitment to architectural state in a microprocessor
Method and hardware apparatus are disclosed for reducing the rollback penalty on exceptions in a microprocessor executing traces of scheduled instructions. Speculative state is committed to the...
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7496734 |
System and method for handling register dependency in a stack-based pipelined processor
There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor; 2)...
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7493471 |
Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready
A method for synchronized renaming between a master processor and a coprocessor includes sending from the master processor an operation for execution by the coprocessor along with an identifier, at...
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7490226 |
Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor
A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial...
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7490225 |
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number
Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in...
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7487337 |
Back-end renaming in a continual flow processor pipeline
The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands. ...
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7487336 |
Method for register allocation during instruction scheduling
The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands.
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7484069 |
Watchpointing unaligned data accesses
A data processing system incorporating watchpoint registers is provided. The memory accesses to be detected may be unaligned memory accesses. The watchpoint may operate in a normal mode and also in...
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7475226 |
System for managing data dependency using bit field instruction destination vector identifying destination for execution results
A method of data processing includes fetching a sequence of instructions, assigning each instruction within the sequence a respective unique instruction tag, and associating a respective...
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7475224 |
Register map unit supporting mapping of multiple register specifier classes
Embodiments of this invention relate to sharing resources on a semiconductor between multiple functional units to reduce the number of register rename mappers and particularly to providing a way to...
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7464242 |
Method of load/store dependencies detection with dynamically changing address length
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming...
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7454598 |
Controlling out of order execution pipelines issue tagging
A method and system of controlling out of order execution pipelines using issue tags is disclosed. The issue tags are used to dynamically calculate pipeline skew parameters that track the relative...
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7434032 |
Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators
A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers...
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7434031 |
Execution displacement read-write alias prediction
RAW aliasing can be predicted with register bypassing based at least in part on execution displacement alias prediction. Repeated aliasing between read and write operations (e.g., within a loop),...
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7430654 |
Dynamic instruction dependency monitor and control system
Method and system for controlling the dynamic latency of an arithmetic logic unit (ALU). In one embodiment, the identification of the destination operand of an instruction is stored in a temporary...
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7428631 |
Apparatus and method using different size rename registers for partial-bit and bulk-bit writes
An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both...
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7424595 |
System for managing circuitry of variable function information processing circuit and method for managing circuitry of variable function information processing circuit
Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA ( 12 ) is stored in a memory ( 13 ), the configuration management...
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7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers
There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code...
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7418575 |
Long instruction word processing with instruction extensions
A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of...
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7412592 |
Branch instruction control apparatus and control method
The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch...
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7409503 |
Register file systems and methods for employing speculative fills
Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that...
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7409500 |
Systems and methods for employing speculative fills
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data...
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7406587 |
Method and system for renaming registers in a microprocessor
A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the...
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7406565 |
Multi-processor systems and methods for backup for non-coherent speculative fills
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with...
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7398375 |
Technique for reduced-tag dynamic scheduling and reduced-tag prediction
The present invention provides a dynamic scheduling scheme that uses reservation stations having at least one station that stores an at least two operand instruction. An allocator portion...
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7383422 |
Very long instruction word (VLIW) computer having an efficient instruction code format
A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a...
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7383409 |
Cache systems and methods for employing speculative fills
One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in...
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7380104 |
Method and apparatus for back to back issue of dependent instructions in an out of order issue queue
A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following...
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7376816 |
Method and systems for executing load instructions that achieve sequential load consistency
A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory...
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7376794 |
Coherent signal in a multi-processor system
Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source...
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7373484 |
Controlling writes to non-renamed register space in an out-of-order execution microprocessor
A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes...
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7370178 |
Method for latest producer tracking in an out-of-order processor, and applications thereof
Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location...
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7370176 |
System and method for high frequency stall design
A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction...
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7366719 |
Method for the manipulation, storage, modeling, visualization and quantification of datasets
There is described a method for manipulation, storage, modeling, visualization, and quantification of datasets, which correspond to target strings. An iterative algorithm is used to generate...
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7363469 |
Method and system for on-demand scratch register renaming
A method and processor for performing on-demand scratch register reallocation by dynamically adjusting the number of scratch registers from within the pool of rename registers includes initially...
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7363468 |
Load address dependency mechanism system and method in a high frequency, low power processor system
The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At...
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7360066 |
Boolean processor
A processor including a Boolean logic unit, wherein the Boolean logic unit is operable for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, a...
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7360063 |
Method for SIMD-oriented management of register maps for map-based indirect register-file access
A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each...
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