|
Match
|
Document |
Document Title |
|
|
7620798 |
Latency tolerant pipeline synchronization
A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction...
|
|
|
7617387 |
Methods and system for resolving simultaneous predicted branch instructions
A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions,...
|
|
|
7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
|
|
|
7603527 |
Resolving false dependencies of speculative load instructions
Methods and apparatus for resolving false dependencies associated with speculatively executing load instructions in a processor core are described. In one embodiment, physical addresses of a load...
|
|
|
7600098 |
Method and system for efficient implementation of very large store buffer
A method and system for efficient implementation of a large store buffer within a processor includes a store buffer within a processor having a first component configured to hold a plurality of...
|
|
|
7600097 |
Detecting raw hazards in an object-addressed memory hierarchy by comparing an object identifier and offset for a load instruction to object identifiers and offsets in a store queue
One embodiment of the present invention provides a system that processes memory-access instructions in an object-addressed memory hierarchy. During operation, the system receives a load instruction...
|
|
|
7594227 |
Dependency graph parameter scoping
A number of tasks are defined according to a dependency graph. Multiple parameter contexts are maintained, each associated with a different scope of the tasks. A parameter used in a first of the...
|
|
|
7594097 |
Microprocessor output ports and control of instructions provided therefrom
A method and apparatus are provided for controlling instructions provided by a microprocessor output port to other execution units. A microprocessor pipeline of instructions is provided for each...
|
|
|
7590826 |
Speculative data value usage
A data processing system 2 utilizes a register renaming mechanism 10, 26 to rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The...
|
|
|
7590825 |
Counter-based memory disambiguation techniques for selectively predicting load/store conflicts
Memory access management techniques are described. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations...
|
|
|
7580914 |
Method and apparatus to improve execution of a stored program
In one embodiment, the invention provides a method comprising determining metadata encoded in instructions of a stored program; and executing the stored program based on the metadata.
|
|
|
7568197 |
Method and apparatus for interposing kernel symbols
In general, the invention relates to a method for loading a kernel module. The method involves loading a preload module into a kernel. Loading the preload module includes creating a dynamic...
|
|
|
7562206 |
Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions
Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are...
|
|
|
7555634 |
Multiple data hazards detection and resolution unit
Order indication logic can be recycled for at least two different data hazards, thus reducing the amount of processor real estate consumed by data hazard resolution logic. The logic also allows a...
|
|
|
7552247 |
Increased computer peripheral throughput by using data available withholding
A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and...
|
|
|
7530072 |
Method to segregate suspicious threads in a hosted environment to prevent CPU resource exhaustion from hung threads
A system and method for segregating suspicious threads in a hosted environment to prevent CPU resource exhaustion from hung threads are disclosed. An application server identify suspicious threads...
|
|
|
7526634 |
Counter-based delay of dependent thread group execution
Systems and methods for synchronizing processing work performed by threads, cooperative thread arrays (CTAs), or “sets” of CTAs. A central processing unit can load launch commands for a first...
|
|
|
7523295 |
Processor and method of grouping and executing dependent instructions in a packet
An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a...
|
|
|
7523266 |
Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level
One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor....
|
|
|
7502888 |
Symmetric multiprocessor system
Systems, methods, and device are provided for symmetric multiprocessor (SMP) systems. One method embodiment includes creating a child process for each processor in the SMP. An event address...
|
|
|
7496921 |
Processing block with integrated light weight multi-threading support
A processing block is equipped with a storage to facilitate storage and maintenance of a thread switching structure to provide multi-threading support in a light-weight manner. In various...
|
|
|
7496899 |
Preventing loss of traced information in a data processing apparatus
Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided. The data...
|
|
|
7496735 |
Method and apparatus for incremental commitment to architectural state in a microprocessor
Method and hardware apparatus are disclosed for reducing the rollback penalty on exceptions in a microprocessor executing traces of scheduled instructions. Speculative state is committed to the...
|
|
|
7493471 |
Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready
A method for synchronized renaming between a master processor and a coprocessor includes sending from the master processor an operation for execution by the coprocessor along with an identifier, at...
|
|
|
7493447 |
System and method for caching sequential programs
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
|
|
|
7490225 |
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number
Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in...
|
|
|
7487380 |
Execution recovery escalation policy
Deterministic code execution may be recovered for programs or portions thereof by implementing a programmable policy on a system host to escalate the scope of a code discard based on various...
|
|
|
7487337 |
Back-end renaming in a continual flow processor pipeline
The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands. ...
|
|
|
7487336 |
Method for register allocation during instruction scheduling
The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands.
|
|
|
7480771 |
Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged
We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated,...
|
|
|
7478226 |
Processing bypass directory tracking system and method
A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural...
|
|
|
7475399 |
Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization
According to a method of operating a data processing system, one or more monitoring parameter sets are established in a processing unit within the data processing system. The processing unit...
|
|
|
7469407 |
Method for resource balancing using dispatch flush in a simultaneous multithread processor
The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared...
|
|
|
7464253 |
Tracking multiple dependent instructions with instruction queue pointer mapping table linked to a multiple wakeup table by a pointer
A method and apparatus for improving the operation of an out-of order computer processor by utilizing and managing instruction wakeup using pointers with an instruction queue payload random-access...
|
|
|
7464242 |
Method of load/store dependencies detection with dynamically changing address length
A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming...
|
|
|
7461238 |
Simple load and store disambiguation and scheduling at predecode
Embodiments of the invention provide a method for executing instructions. In one embodiment, the method includes receiving a load instruction and a store instruction to be executed in a processor...
|
|
|
7454599 |
Selecting multiple threads for substantially concurrent processing
The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for...
|
|
|
7454598 |
Controlling out of order execution pipelines issue tagging
A method and system of controlling out of order execution pipelines using issue tags is disclosed. The issue tags are used to dynamically calculate pipeline skew parameters that track the relative...
|
|
|
7451295 |
Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues
One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests...
|
|
|
7451294 |
Apparatus and method for two micro-operation flow using source override
A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single...
|
|
|
7448037 |
Method and data processing system having dynamic profile-directed feedback at runtime
Software communicates to a processing unit a classification each of at least one schedulable software entity that the processing unit executes. A resource manager within the processing unit...
|
|
|
7441107 |
Utilizing an advanced load address table for memory disambiguation in an out of order processor
Embodiments include a system for minimizing storage space required for tracking load instructions through a pipeline in a processor. Store instructions are tracked in a separate queue and only load...
|
|
|
7434002 |
Utilizing cache information to manage memory access and cache utilization
In a method of optimizing utilization of a shared cache, a set of locations in the cache is probed. The probing takes place while an observed process is running, descheduled, or interrupted. It is...
|
|
|
7430653 |
Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking
A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource...
|
|
|
7430651 |
System and method for assigning tags to control instruction processing in a superscalar processor
A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each...
|
|
|
7428631 |
Apparatus and method using different size rename registers for partial-bit and bulk-bit writes
An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both...
|
|
|
7421567 |
Using a modified value GPR to enhance lookahead prefetch
The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction...
|
|
|
7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers
There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code...
|
|
|
7418625 |
Deadlock detection and recovery logic for flow control based data path design
Certain embodiments of the invention may be found in a method and system for handling deadlock conditions in a data processing system. Aspects of the method may comprise identifying a potential...
|
|
|
7418552 |
Memory disambiguation for large instruction windows
A memory disambiguation apparatus includes a store queue, a store forwarding buffer, and a version count buffer. The store queue includes an entry for each store instruction in the instruction...
|