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9043773 Identification and management of unsafe optimizations  
Techniques for implementing identification and management of unsafe optimizations are disclosed. A method of the disclosure includes receiving, by a managed runtime environment (MRE) executed by a...
8990335 Continuous full scan data store table and distributed data store featuring predictable answer time for unpredictable workload  
A method for storing and retrieving data in a storage node of a data store and storage node of a data store, storing in main-memory at least one segment of a relational table. The storage node...
8984261 Store data forwarding with no memory model restrictions  
Embodiments relate to loading data in a pipelined microprocessor. An aspect includes issuing a load request that comprises a load address requiring at least one block of data the same size as a...
8984264 Precise data return handling in speculative processors  
The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing...
8977837 Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes  
At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second...
8966229 Systems and methods for handling instructions of in-order and out-of-order execution queues  
Processing systems and methods are disclosed that can include an instruction unit which provides instructions for execution by the processor; a decode/issue unit which decodes instructions...
8959314 MFENCE and LFENCE micro-architectural implementation method and system  
A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions...
8959527 Dependency management in task scheduling  
A task is marked as dependent upon a preceding task. The task that is attempted to be taken for execution from a head of a pending task queue that is marked is deferred. The deferred task is...
8954985 Dependency management in task scheduling  
A task is marked as dependent upon a preceding task. The task that is attempted to be taken for execution from a head of a pending task queue that is marked is deferred. The deferred task is...
8935513 Processor performance improvement for instruction sequences that include barrier instructions  
A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following...
8933953 Managing active thread dependencies in graphics processing  
A scoreboard for a video processor may keep track of only dispatched threads which have not yet completed execution. A first thread may itself snoop for execution of a second thread that must be...
8924691 Software pipelining  
A software pipelining method for generating a schedule for executing a plurality of instructions on a processor, the plurality of instructions involving one or more variables, the processor having...
8918625 Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison  
A processor that executes instructions out of program order is described. In some implementations, a processor detects whether a second memory operation is dependent on a first memory operation...
8918624 Scaling and managing work requests on a massively parallel machine  
A method, computer program product and computer system for scaling and managing requests on a massively parallel machine, such as one running in MIMD mode on a SIMD machine. A submit mux...
8914806 Information processing apparatus and virtual storage management method, and storage medium for restriction on process swapping based on process attributes and processor utilization  
A virtual storage management method that can increase the overall processing speed while preventing a processor from being overloaded. A request for acquisition of a memory area in a primary...
8914616 Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed  
A data processing apparatus and method are provided. A processor performs data processing operations in response to data processing instructions which reference logical registers. A set of...
8904150 Microprocessor systems and methods for handling instructions with multiple dependencies  
A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues...
8898440 Request control device, request control method and associated processors  
A request control device, request control method, and a multiprocessor cooperation architecture. The request control device is connected to a request storage module and includes a comparing means...
8881265 Computer system, computer system control method, computer system control program, and integrated circuit  
A computer system includes a memory having a secure area and a plurality of processors using the memory. When an access-allowed program unit executed by one of the processors starts an access to...
8874879 Vector processing circuit, command issuance control method, and processor system  
A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline...
8838906 Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution  
In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory,...
8838939 Debugging multithreaded code by generating exception upon target address CAM search for variable and checking race condition  
Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system,...
8839253 System and method for load-adaptive mutual exclusion with waiting process counts  
A system and associated method for mutually exclusively executing a critical section by a process in a computer system. The critical section accessing a shared resource is controlled by a lock....
8832671 Conflict-free register allocation  
One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather...
8812823 Memory disambiguation techniques using counter ratio to selectively disable load/store conflict prediction  
A memory access management technique is disclosed, one embodiment of which relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target...
8806178 Set sampling controls instruction  
A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the...
8793471 Atomic program verification  
An apparatus for executing an atomic memory transaction comprises a processing core in a multi-processing core system, where the processing core is configured to store an atomic program in a cache...
8788794 Programmable atomic memory using stored atomic procedures  
A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets...
8782434 System and method for validating program execution at run-time  
A pipelined processor comprising a cache memory system, fetching instructions for execution from a portion of said cache memory system, an instruction commencing processing before a digital...
8782435 System and method for validating program execution at run-time using control flow signatures  
A processor comprising: an instruction processing pipeline, configured to receive a sequence of instructions for execution, said sequence comprising at least one instruction including a flow...
8762620 Multiprocessor storage controller  
A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In...
8756374 Store queue supporting ordered and unordered stores  
Some described embodiments provide a system that performs stores in a memory system. During operation, the system receives a store for a first thread. The system then creates an entry for the...
8745360 Generating predicate values based on conditional data dependency in vector processors  
Embodiments of a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency...
8707015 Reclaiming physical registers renamed as microcode architectural registers to be available for renaming as instruction set architectural registers based on an active status indicator  
A method of operating a processor includes reclaiming a physical register renamed as a microcode architectural register used by a microcode routine. The physical register is reclaimed according to...
8688963 Checkpoint allocation in a speculative processor  
The embodiments described in the instant application provide a system for generating checkpoints. In the described embodiments, while speculatively executing instructions with one or more...
8683179 Method and apparatus for performing store-to-load forwarding from an interlocking store using an enhanced load/store unit in a processor  
A method and a processor load/store unit (LSU) are described for performing store-to-load forwarding (STLF) from an interlocking store. STLF is performed when a starting address of the store and...
8656102 Method for preloading configurations of a reconfigurable heterogeneous system for information processing into a memory hierarchy  
A method for preloading into a hierarchy of memories, bitstreams representing the configuration information for a reconfigurable processing system including several processing units. The method...
8656144 Image processing device, image processing method, and image processing program  
The invention provides an image processing device, an image processing method, and an image processing program which enable accurately observing a moving image of an object within a time interval...
8635436 Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall  
During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish...
8627044 Issuing instructions with unresolved data dependencies  
The described embodiments include a processor that determines instructions that can be issued based on unresolved data dependencies. In an issue unit in the processor, the processor keeps a record...
8615644 Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition  
A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily...
8612728 Reducing data hazards in pipelined processors to provide high processor utilization  
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on...
8601240 Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative execution  
The described embodiments provide a system for executing instructions in a processor. While executing instructions in an execute-ahead mode, the processor encounters a store instruction for which...
8601177 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8589662 Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals  
A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program...
8583901 Register renaming system using multi-bank physical register mapping table and method thereof  
Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to...
8578136 Apparatus and method for mapping architectural registers to physical registers  
An apparatus and method are provided for performing register renaming, whereby architectural registers from a set of architectural registers are mapped to physical registers from a set of physical...
8566567 System to profile and optimize user software in a managed run-time environment  
Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture...
8560813 Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision  
A method and apparatus are provided for executing instructions from a plurality of instruction threads on a multi-threaded processor. The instruction threads may each include instructions of...
8555035 Conflict-free register allocation using a multi-bank register file with input operand alignment  
One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather...