Matches 401 - 450 out of 532 < 1 2 3 4 5 6 7 8 9 10 11 >
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5838944 System for storing processor register data after a mispredicted branch  
A system for recovering most recent writer status when a mispredicted branch occurs in a processor that executes instructions out of order. A queue holds instructions stored in the order they are...
5838941 Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers  
An advanced register renamer comprises an associative memory having a plurality of entries, each entry storing a representation of a single operation as an expression paired with a corresponding...
5835745 Hardware instruction scheduler for short execution unit latencies  
A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions,...
5835747 Hierarchical scan logic for out-of-order load/store execution control  
Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in...
5835949 Method of identifying and self-modifying code  
A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the...
5826096 Minimal instruction set computer architecture and multiple instruction issue method  
A minimal instruction set computer architecture (hyperscalar computer architecture) comprises a central memory, an instruction buffer, a control unit, an I/O control unit, a plurality of functional...
5812812 Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue  
A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In...
5812810 Instruction coding to support parallel execution of programs  
A computer system with multiple execution boxes operates by assigning serial numbers to each instruction in a set of linearly dependent computer instructions and then rearranging those instructions...
5812811 Executing speculative parallel instructions threads with forking and inter-thread communication  
A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the...
5809275 Store-to-load hazard resolution system and method for a processor that executes instructions out of order  
A store-to-load (ST/LD) hazard resolution system for resolving conflicts produced from ST/LD instruction dependencies and out of order execution of instructions in a processor. The ST/LD hazard...
5805849 Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions  
A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data...
5805876 Method and system for reducing average branch resolution time and effective misprediction penalty in a processor  
Logic circuitry provides a fast resolution of conditional branch instructions in a high-performance superscalar processor. The logic circuitry facilities early (fast) resolution of a subset of...
5805851 System for determining data dependencies among intra-bundle instructions queued and prior instructions in the queue  
A method for determining intra-bundle dependencies includes a step of pre-inserting target registers of inserting instructions into slots of an instruction queue. The target registers of the...
5802338 Method of self-parallelizing and self-parallelizing multiprocessor using the method  
An apparatus and method for self-parallelizing and executing a sequence of instructions. During a first mode of operation, instructions are executed concurrently with the parallelizing of...
5802374 Synchronizing parallel processors using barriers extending over specific multiple-instruction regions in each instruction stream  
A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i.e. it includes several instructions in each instruction stream. None of the processors performing related tasks can...
5799179 Handling of exceptions in speculative instructions  
CPU overhead is minimized through tracking speculative exceptions (202) for later processing during exception resolution (204) including pointing to the addresses of these speculative instructions,...
5799165 Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay  
A superscalar microprocessor includes a scheduler which contains storage for information related to operations and scan logic for selecting operations for out-of-order execution by a set of...
5799167 Instruction nullification system and method for a processor that executes instructions out of order  
An instruction nullification system facilitates handling of nullification dependencies in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch...
5799166 Window delta from current window for fast register file address dependency checking  
A simplified comparison of register designations by using a window delta which indicates how much the window of an instruction differs from the current window register designation. Where registers...
5797025 Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branching  
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic...
5790826 Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes  
The dispatch unit of a superscalar processor checks for register dependencies among instructions to be issued together as a group. The first instruction's destination register is compared to the...
5790822 Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor  
A method and apparatus for executing instructions in a pipelined microprocessor. The method includes re-ordering the set of instructions prior to loading the instructions into an instruction cache....
5790827 Method for dependency checking using a scoreboard for a pair of register sets having different precisions  
A dependency checking method includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each single precision register maps to an...
5787266 Apparatus and method for accessing special registers without serialization  
A microprocessor employing an apparatus for performing special register writes without serialization is provided. The apparatus detects special register write instructions when the instructions are...
5784587 Method and system for recovering from cache misses  
A recovery method for each instruction in an instruction queue comprises steps of monitoring a launch bus to determine when an instruction has executed and comparing the tag number of the launched...
5784639 Load buffer integrated dynamic decoding logic  
A novel method to quickly decode a block-code in a load buffer and compare it against multiple wake-up signals in an out-of-order processor. A block-code is used to describe the blocking condition...
5784586 Addressing method for executing load instructions out of order with respect to store instructions  
A method of permitting out of order execution of load instructions with respect to older store instructions in a general purpose computer evaluates whether the same data bytes are being accessed by...
5784588 Dependency checking apparatus employing a scoreboard for a pair of register sets having different precisions  
A dependency checking apparatus includes a scoreboard which records destination operands of instructions outstanding within the pipeline of a microprocessor. Each single precision register maps to...
5781752 Table based data speculation circuit for parallel processing computer  
A predictor circuit permits advanced execution of instructions depending for their data on previous instructions by predicting such dependencies based on previous mis-speculations detected at the...
5778210 Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time  
A method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time allows components within the processor to begin...
5774687 Central processing unit detecting and judging whether operation result executed by ALU in response to a first instruction code meets a predetermined condition  
A central processing unit in a microprocessor, or the like, executes at high speed a simple program and sets a different immediate depending on a true or false state of a predetermined condition....
5768556 Method and apparatus for identifying dependencies within a register  
An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register...
5768555 Reorder buffer employing last in buffer and last in line bits  
A reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction...
5764943 Data path circuitry for processor having multiple instruction pipelines  
A superscalar processor has two pipelines that include decode, operand read, execute and writeback stages. An instruction datapath circuit of the processor comprises a plurality of result buses...
5764942 Method and system for selective serialization of instruction processing in a superscalar processor system  
The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of...
5765017 Method and system in a data processing system for efficient management of an indication of a status of each of multiple registers  
A method and system in a data processing system are disclosed for efficiently managing an indication of a status of each of a plurality of registers included with the data processing system. An...
5765035 Recorder buffer capable of detecting dependencies between accesses to a pair of caches  
A dependency checking structure is provided which compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode...
5754813 Data processor  
Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having...
5754812 Out-of-order load/store execution control  
Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in...
5751984 Method and apparatus for simultaneously executing instructions in a pipelined microprocessor  
An instruction combination unit for a microprocessor compares multiple fetched instructions to determine whether they can be combined for simultaneous execution. The instruction combination unit...
5751983 Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations  
A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by...
5752013 Method and apparatus for providing precise fault tracing in a superscalar microprocessor  
A superscalar processor with a precise fault mechanism. Instructions are grouped into a cluster of instructions to be executed simultaneously by the superscalar processor. The cluster is formed...
5748935 Reconstruction of young bits in annex after mispredicted execution branch in pipelined processor  
In a pipelined processor, a method and apparatus for performing restoration of the previous values of young bits in the annex after a mispredicted branch has been detected. In a first embodiment,...
5748978 Byte queue divided into multiple subqueues for optimizing instruction selection logic  
An apparatus for aligning variable byte length instructions to a plurality of issue positions is provided. The apparatus includes a byte queue divided into several subqueues. Each subqueue is...
5745726 Method and apparatus for selecting the oldest queued instructions without data dependencies  
An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of...
5745780 Method and apparatus for source lookup within a central processing unit  
A method and apparatus for looking up source matches in a central processing unit (CPU) is utilized to identify dependencies between instructions that have been renamed via buffer renaming...
5737629 Dependency checking and forwarding of variable width operands  
A pipelined or superscalar processor (10) that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand (200) into...
5737562 CPU pipeline having queuing stage to facilitate branch instructions  
A pipelined microprocessor is provided with a queuing stage between an instruction fetch stage and an instruction decode stage to facilitate branch instructions and to receive instructions from the...
5729757 Super-computer system architectures using status memory to alter program  
A computer system is disclosed in which instruction sequencing is under the control of a program control computer, but each individual instruction is assigned for execution to an individual...
5721854 Method and apparatus for dynamic conversion of computer instructions  
An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is...
Matches 401 - 450 out of 532 < 1 2 3 4 5 6 7 8 9 10 11 >