Matches 351 - 400 out of 532 < 1 2 3 4 5 6 7 8 9 10 11 >
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5996063 Management of both renamed and architected registers in a superscalar computer system  
The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain...
5996064 Method and apparatus for guaranteeing minimum variable schedule distance by using post-ready latency  
A method for guaranteeing minimum variable scheduling distance between instructions in a processor includes receiving a plurality of instructions and determining the post-ready latency of each...
5991884 Method for reducing peak power in dispatching instructions to multiple execution units  
A method of reducing microprocessor peak power by scheduling execution of instructions to multiple execution units. In the prior art, parallel processing of instructions by high-power execution...
5991870 Processor for executing an instructions stream where instruction have both a compressed and an uncompressed register field  
A processor that executes an instruction stream having at least one compressed register field allows for smaller programs and greater processing speed. The instructions have at least one n-bit...
5987595 Method and apparatus for predicting when load instructions can be executed out-of order  
The invention in several embodiments includes an apparatus and a method for predicting whether store instructions can be safely executed out-of-order. The apparatus, includes at least one execution...
5987594 Apparatus for executing coded dependent instructions having variable latencies  
A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a...
5983335 Computer system having organization for multiple condition code setting and for testing instruction out-of-order  
Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction...
5983341 Data processing system and method for extending the time for execution of an instruction  
A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the...
5978900 Renaming numeric and segment registers using common general register pool  
A microprocessor capable of renaming a numeric register and a segment register includes a plurality of general registers and a data dependency unit. The data dependency unit is configured to...
5964867 Method for inserting memory prefetch operations based on measured latencies in a program optimizer  
A method is provided for optimizing a program by inserting memory prefetch operations in the program executing in a computer system. The computer system includes a processor and a memory. Latencies...
5961633 Execution of data processing instructions  
Data processing apparatus in which successive data processing instructions are executed comprises: memory accessing means for accessing a data memory in response to one or more of the instructions,...
5961634 Reorder buffer having a future file for storing speculative instruction execution results  
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently...
5958043 Superscalar processor with forward map buffer in multiple instruction parallel issue/execution management system  
A multiple instruction parallel issue/execution management system including a forward map buffer for storing forward map information indicating whether or not the result value generated by...
5951670 Segment register renaming in an out of order processor  
A processor for executing a plurality of instructions. The processor comprises a plurality of logical segment registers, wherein the logical segment registers define an architectural state for...
5941983 Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues  
A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between...
5937195 Global control flow treatment of predicated code  
The relationships among predicates are tracked globally by uniformly treating both control flow and explicit predicates by mapping them to a single connected partition graph. This allows for the...
5931957 Support for out-of-order execution of loads and stores in a processor  
To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed...
5930821 Method and apparatus for shared cache lines in split data/code caches  
An apparatus and method for sharing cache lines within a split data/code cache is provided. The invention utilizes cache snoop and state control, coupled to both a data cache and a code cache,...
5930832 Apparatus to guarantee TLB inclusion for store operations  
A computer system includes a processor and a cache and memory management unit. The processor includes a means for retiring instructions in program order. The cache and memory management unit...
5930492 Rapid pipeline control using a control word and a steering word  
A pipeline conveys a control word and a steering word with each instruction. The control word specifies the control signals for the instruction at each pipeline stage. The steering word specifies...
5923863 Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination  
Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled...
5920710 Apparatus and method for modifying status bits in a reorder buffer with a large speculative state  
A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. To reduce the time delay for identifying mispredicted instructions, prioritizing...
5918032 Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions  
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
5918034 Method for decoupling pipeline stages  
The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination...
5907714 Method for pipelined data processing with conditioning instructions for controlling execution of instructions without pipeline flushing  
A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to...
5903739 System and method for processing load instruction in accordance with "no-fault" processing facility including arrangement for preserving access fault indicia  
A microprocessor in a computer system processes an instruction stream comprising instructions of a plurality of instruction types including an information retrieval instruction type. The...
5901308 Software mechanism for reducing exceptions generated by speculatively scheduled instructions  
A method of compiling an application to reduce the occurrence of speculative exceptions is described. The method includes the steps of compiling the application to provide a speculation table and...
5898853 Apparatus for enforcing true dependencies in an out-of-order processor  
In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an...
5894582 Method of controlling parallel processing at an instruction level and processor for realizing the method  
Apparatus for realizing instruction level parallel processing includes an instruction buffer for storing instructions fetched from a memory until the instructions are sent from the instruction...
5894576 Method and apparatus for instruction scheduling to reduce negative effects of compensation code  
A method is described for scheduling an instruction of a computer program. The instruction is scheduled into an active block of the computer program if no compensation copy is necessary, or if any...
5892936 Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register  
A superscalar microprocessor configured to speculatively generate register values associated with a particular register is provided. Multiple register values are generated in parallel, wherein each...
5893121 System and method for swapping blocks of tagged stack entries between a tagged stack cache and an untagged main memory storage  
A computer system has a CPU, a stack cache and a main memory. The main memory is a conventional untagged memory, where each memory location is a word having a bit size that is an integer power of 2...
5887185 Interface for coupling a floating point unit to a reorder buffer  
A microprocessor has an interface between a reorder buffer and a floating point unit, including a retire signal provided by the reorder buffer and a valid signal provided by the floating point...
5887174 System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by the rescheduling of idle slots  
Instructions are scheduled for execution by a processor having a lookahead buffer by identifying an idle slot in a first instruction schedule of a first basic block of instructions, and by...
5881262 Method and apparatus for blocking execution of and storing load operations during their execution  
A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present...
5878242 Method and system for forwarding instructions in a processor with increased forwarding probability  
A system and method for forwarding a first instruction into a second instruction in a processor is disclosed. The processor comprises an execution unit and providing a plurality of instructions....
5878252 Microprocessor configured to generate help instructions for performing data cache fills  
A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a...
5872949 Apparatus and method for managing data flow dependencies arising from out-of-order execution, by an execution unit, of an instruction series input from an instruction source  
An apparatus and method to manage data flow dependencies so that a processor can complete instructions and write associated data to architected logical registers out of the program order. This...
5870576 Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures  
Methods apparatus for storing and expanding wide instruction words in a computer system are provided. The computer system includes a memory and an instruction cache. Compressed instruction words of...
5867684 Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction  
A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store...
5864692 Method and apparatus for protecting memory-mapped devices from side effects of speculative instructions  
A computer system includes a CPU for executing conventional instructions and speculative instructions, and a memory controller coupled to a system bus. In response to an access operation by one of...
5854914 Mechanism to improved execution of misaligned loads  
A method and apparatus for executing a misaligned load. The method begins with receiving a load request to load data from a first memory location. An entry in a store buffer is tested to determine...
5850552 Optimization apparatus for removing hazards by arranging instruction order  
An optimization apparatus is provided for removing hazards from a program by rearranging instructions for each program segment. The apparatus comprises: a Directed Acyclic Graph (DAG) generating...
5850533 Method for enforcing true dependencies in an out-of-order processor  
In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an...
5848256 Method and apparatus for address disambiguation using address component identifiers  
A scheduling unit is described for scheduling an execution order of a first instruction of a first type and a second instruction of a second type in an instruction stream where the second...
5848287 Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches  
A superscalar microprocessor is provided which maintains coherency between a pair of caches accessed from different stages of an instruction processing pipeline. A dependency checking structure is...
5845103 Computer with dynamic instruction reuse  
A computer architecture allowing reuse of previously determined instruction results, indexes instruction results according to instruction addresses. The continued validity of operand values in...
5842036 Circuit and method for scheduling instructions by predicting future availability of resources required for execution  
An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for...
5838940 Method and apparatus for rotating active instructions in a parallel data processor  
In a microprocessor, apparatus and method coordinate the fetch and issue of instructions by rotating multiple, fetched instructions into an issue order prior to issuance and dispatching selected of...
5838896 Central processing unit for preventing program malfunction  
An improved CPU for preventing a program malfunction which is capable of preventing a malfunction of a program by resetting the CPU when an abnormal data is fetched from a memory due to a noise,...
Matches 351 - 400 out of 532 < 1 2 3 4 5 6 7 8 9 10 11 >