Matches 251 - 300 out of 532 < 1 2 3 4 5 6 7 8 9 10 11 >
Match Document Document Title
6457118 Method and system for selecting and using source operands in computer system instructions  
According to the present invention, techniques for setting selected operand fields in pipelined architectures are provided. Methods and systems for efficiently selecting operand fields according to...
6449710 Stitching parcels  
The invention provides a method and system for performing instructions in a microprocessor having a set of registers, in which instructions which operate on portions of a register are recognized,...
6446194 Virtual register renamed instruction issue for execution upon virtual/physical rename buffer wrap around detection signaling available physical register  
A method for wrap detection in a microprocessor system, the system including a plurality of rename buffers. The method includes performing a two's complement subtraction of a completion pointer...
6442673 Update forwarding cache for address mode  
An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor having design characteristics-complexity, power, and timing-that are not...
6442677 Apparatus and method for superforwarding load operands in a microprocessor  
An apparatus and method for superforwarding load operands in a microprocessor are provided. An execution unit in a microprocessor is configured to receive a load instruction and a subsequent...
6438681 Detection of data hazards between instructions by decoding register indentifiers in each stage of processing system pipeline and comparing asserted bits in the decoded register indentifiers  
A computer system utilizing a processing system capable of efficiently comparing register identifiers to detect data hazards between instructions of a computer program is used to execute the...
6430683 Processor and method for just-in-time delivery of load data via time dependency field  
A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an...
6412066 Microprocessor employing branch instruction to set compression mode  
A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length...
6412061 Dynamic pipelines with reusable logic elements controlled by a set of multiplexers for pipeline stage selection  
A method of dynamically adjusting a multiple stage pipeline to execute one of a set of instructions, wherein each stage has a latency and performs a selected data operation. An instruction to be...
6408378 Multi-bit scoreboarding to handle write-after-write hazards and eliminate bypass comparators  
An apparatus and method of multi-bit scoreboarding to handle write-after-write hazards and eliminate bypass comparators. The method comprises providing a set of data storage units that include a...
6408372 Data processing control device  
A RAM ( 12 ) used by the CPU comprises a work buffer ( 14 ) and a work register ( 151 ) for pipelined processing. The work buffer ( 14 ) consists of the first to fourth work buffers ( 141 to 144...
6405304 Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list  
A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of...
6393552 Method and system for dividing a computer processor register into sectors  
A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into...
6381689 Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction  
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently...
6381691 Method and apparatus for reordering memory operations along multiple execution paths in a processor  
A method is provided for scheduling instructions for execution along multiple paths in a Computer processing system implementing out-of-order execution. The method includes the step of selecting...
6378062 Method and apparatus for performing a store operation  
The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by...
6367003 Digital signal processor having enhanced utilization of multiply accumulate (MAC) stage and method  
A digital signal processor (DSP) architecture which allows the DSP Multiply-Accumulator (MAC) to be used for special fixed functions during those times when the programmable portions of the DSP are...
6363441 TIMING CONTROLLER HAVING DEPENDENCY MEMORY, SELECTION SERIALIZATION COMPONENT AND REORDERING COMPONENT FOR MAINTAINING TIME DEPENDENCIES IN CONVERSIONS BETWEEN SEQUENTIAL AND PARALLEL OPERATIONS USING STAGING MEMORY  
An electronic system and method that maintains time dependencies and ordering constraints in an electronic system. A timing controller utilizes a representative bit to track timing dependencies...
6363474 Process switching register replication in a data processing system  
In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be...
6360315 Method and apparatus that supports multiple assignment code  
The present invention is an apparatus that supports multiple assignment code, comprising a register that may be assigned multiple values, instructions that receive a value and dispatch a result, a...
6351803 Mechanism for power efficient processing in a pipeline processor  
A processor including a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. A pipefile having at least the same number of entries...
6351455 System test metacontroller  
A system test metacontroller including an input device and a processor. The input device accepts a metascript containing commands to control devices which are part of a test arrangement. At least...
6351802 Method and apparatus for constructing a pre-scheduled instruction cache  
A method of scheduling instructions in a computer processor. The method comprises fetching instructions to create an in-order instruction buffer, and scheduling instruction from the instruction...
6349382 System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order  
In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned...
6345356 Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs  
A dummy instruction is issued, followed by several groups of No Operations (NOPs). The instruction sequencer unit (ISU) detects the dummy instruction and stalls the pipeline until the scoreboard...
6334182 Scheduling operations using a dependency matrix  
A method and apparatus for scheduling operations using a dependency matrix. A child operation, such as a micro-operation, is received for scheduling. The child operation is dependent on the...
6327649 Apparatus for developing internal ROM code using a ROM bus external interface  
An apparatus for developing internal ROM code is disclosed for use in applications where software code is being developed for a ROM device inside a device and there is a need for the application to...
6314560 Method and apparatus for a translation system that aggressively optimizes and preserves full synchronous exception state  
A translating software emulator designed for converting code from a legacy system to a target system and fully preserving the synchronous exception state while still allowing for full and...
6311266 Instruction look-ahead system and hardware  
A method and system for executing instructions in a computer. Each instruction has a look-ahead code indicating the number of instructions after which may be executed before its own execution is...
6308259 Instruction queue evaluating dependency vector in portions during different clock phases  
An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that...
6304955 Method and apparatus for performing latency based hazard detection  
Performing hazard detection in a processor that exhibits register latencies between execution units. The opcode classes of producer and consumer instructions are determined. Using these opcode...
6304953 Computer processor with instruction-specific schedulers  
One embodiment of the present invention is a computer processor that includes a first scheduler adapted to dispatch a first type of computer instructions, and a second scheduler coupled to the...
6298435 Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor  
A method and apparatus for increasing instruction level parallelism using a buffer pointer assignment scheme is implemented whereby rename buffers are assigned during dispatch even though the...
6292884 Reorder buffer employing last in line indication  
A reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction...
6289444 Method and apparatus for subroutine call-return prediction  
A method for associating subroutine calls with corresponding targets includes the step of maintaining a first table of entries. Each entry in the first table includes: a first table first address...
6289442 Circuit and method for tagging and invalidating speculatively executed instructions  
A method and circuit is disclosed for tagging and invalidating speculatively executed instructions. The method includes fetching a first plurality of instructions which includes a conditional...
6286095 Computer apparatus having special instructions to force ordered load and store operations  
A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is...
6282708 Method and processor for structuring a multi-instruction computer program in an internal directed acyclic graph  
A method for structuring a multi-instruction computer program as containing a plurality of basic blocks, that each compose from internal instructions and external jumps organised in an internal...
6279102 Method and apparatus employing a single table for renaming more than one class of register  
In one aspect the present invention provides for an apparatus that includes at least two physical registers and a rename unit to assign at least one of the physical registers to an original...
6266744 Store to load forwarding using a dependency link file  
A processor employing a dependency link file. Upon detection of a load which hits a store for which store data is not available, the processor allocates an entry within the dependency link file for...
6266766 Method and apparatus for increasing throughput when accessing registers by using multi-bit scoreboarding with a bypass control unit  
An apparatus including a set of data storage units having a set of scoreboard bits associated with the set of data storage units; a first execution unit having an output coupled to the data storage...
6266761 Method and system in an information processing system for efficient maintenance of copies of values stored within registers  
A method and system in an information processing system are disclosed for efficiently maintaining copies of values stored within a plurality of registers. The information processing system includes...
6260133 Processor having operating instruction which uses operation units in different pipelines simultaneously  
An instruction fetch unit 10 issues a normal ALU operating instruction or a wide ALU operating instruction using two operating units to a first pipeline 14. The instruction fetch unit 10 also...
6247114 Rapid selection of oldest eligible entry in a queue  
A microprocessor having an instruction queue capable of out-of-order instruction dispatch and rapidly selecting one or more oldest eligible entries is disclosed. The microprocessor may comprise a...
6247121 Multithreading processor with thread predictor  
In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken....
6237082 Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received  
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently...
6216178 Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access execution  
According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command...
6212622 Mechanism for load block on store address generation  
A processor employs ordering dependencies for load instruction operations upon store address instruction operations. The processor divides store operations into store address instruction operations...
6212619 System and method for high-speed register renaming by counting  
A superscalar computer architecture for executing instructions out-of-order, comprising a multiplicity of execution units, a plurality of registers, and a register renaming circuit which generates...
6212623 Universal dependency vector/queue entry  
A processor employs an instruction queue and dependency vectors therein which allow a flexible dependency recording structure. The dependency vector includes a dependency indication for each...
Matches 251 - 300 out of 532 < 1 2 3 4 5 6 7 8 9 10 11 >