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9015720 Efficient state transition among multiple programs on multi-threaded processors by executing cache priming program  
A system and method to optimize processor performance and minimizing average thread latency by selectively loading a cache when a program state, resources required for execution of a program or...
8990767 Parallelization method, system and program  
A method, system, and article of manufacture for solving ordinary differential equations described in a graphical model with nodes as blocks and dependencies as links using the processing of a...
8954714 Processor with cycle offsets and delay lines to allow scheduling of instructions through time  
An apparatus includes a processor. The processor includes two memories. The first memory stores one set of instructions. The second memory stores another set of instructions that are longer than...
8954715 Thread selection for multithreaded processing  
A multithreading processor 4 interleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitry 30 monitors performance...
8924661 Memory system including a controller and processors associated with memory devices  
A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept...
8904152 Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture  
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with...
8874879 Vector processing circuit, command issuance control method, and processor system  
A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline...
8843730 Executing instruction packet with multiple instructions with same destination by performing logical operation on results of instructions and storing the result to the destination  
An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent...
8838906 Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution  
In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory,...
8812822 Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss  
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for minimizing unscheduled D-cache miss pipeline stalls is provided. The...
8788793 Instruction issue to plural computing units from plural stream buffers based on priority in instruction order table  
A processor including L computing units, L being an integer of 2 or greater, the processor comprising: an instruction buffer including M×Z instruction storage areas each storing one instruction, M...
8782434 System and method for validating program execution at run-time  
A pipelined processor comprising a cache memory system, fetching instructions for execution from a portion of said cache memory system, an instruction commencing processing before a digital...
8782435 System and method for validating program execution at run-time using control flow signatures  
A processor comprising: an instruction processing pipeline, configured to receive a sequence of instructions for execution, said sequence comprising at least one instruction including a flow...
8769246 Mechanism for selecting instructions for execution in a multithreaded processor  
In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes...
8756404 Cascaded delayed float/vector execution pipeline  
Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a...
8756406 Method and apparatus for programmable coupling between CPU and co-processor  
In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution...
8732359 Data sharing in high-fidelity simulation and real-time multi-core execution  
When executing a graphical model of a dynamic system that includes two or more concurrently executing sets of operations, a processor is configured to create a first buffer and a second buffer...
8719551 Processor with arbiter sending simultaneously requested instructions from processing elements in SIMD / MIMD modes  
The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the...
8707094 Fault tolerant stability critical execution checking using redundant execution pipelines  
A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the...
8677078 Systems and methods for accessing wide registers  
A device for managing multiple instructions to access multiple wide registers may include logic to receive the multiple instructions to access one of the multiple wide registers, associate each...
8669990 Sharing resources between a CPU and GPU  
A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring...
8661227 Multi-level register file supporting multiple threads  
A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a...
8612728 Reducing data hazards in pipelined processors to provide high processor utilization  
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on...
8601244 Apparatus and method for generating VLIW, and processor and method for processing VLIW  
An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein....
8601177 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8595468 Reverse simultaneous multi-threading  
A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor...
8589634 Processor extensions for accelerating spectral band replication  
Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction...
8533399 Cache directory look-up re-use as conflict check mechanism for speculative memory requests  
In a cache memory, energy and other efficiencies can be realized by saving a result of a cache directory lookup for sequential accesses to a same memory address. Where the cache is a point of...
8533721 Method and system of scheduling out-of-order operations without the requirement to execute compare, ready and pick logic in a single cycle  
A method and system to schedule out of order operations without the requirement to execute compare, ready and pick logic in a single cycle. A lazy out-of-order scheduler splits each scheduling...
8527740 Mechanism of supporting sub-communicator collectives with O(64) counters as opposed to one counter for each sub-communicator  
A system and method for enhancing barrier collective synchronization on a computer system comprises a computer system including a data storage device. The computer system includes a program stored...
8521991 Reducing instruction collisions in a processor  
A technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. In an embodiment, each function unit in a...
8516224 Pipeline replay support for multicycle operations  
Instructions asserted in the instruction pipeline of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline of the...
8484442 Apparatus and method for control processing in dual path processor  
A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of...
8458716 Enterprise resource planning with asynchronous notifications of background processing events  
Methods, systems, and computer program products for operating an enterprise resource planning system. The method includes running a placeholder job in said enterprise resource planning system in...
8448154 Method, apparatus and software for processing software for use in a multithreaded processing environment  
A method, apparatus and software for processing software code for use in a multithreaded processing environment in which lock verification mechanisms are automatically inserted in the software...
8412980 Fault tolerant stability critical execution checking using redundant execution pipelines  
A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the...
8402256 Processing prefix code in instruction queue storing fetched sets of plural instructions in superscalar processor  
The present invention is directed to realize efficient issue of a superscalar instruction in an instruction set including an instruction with a prefix. A circuit is employed which retrieves an...
8397238 Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor  
Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method...
8387065 Speculative popcount data creation  
A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth...
8359462 Method and apparatus for programmable coupling between CPU and co-processor  
In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution...
8327115 Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode  
A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of...
8281054 Methods and apparatus for improved host/initiator utilization in serial advanced technology attachment communication  
Methods and apparatus for improved performance in communications between a SAS/STP initiator device and a plurality of SATA storage devices coupled with the initiator through an enhanced switching...
8255911 System and method for selecting and assigning a basic module with a minimum transfer cost to thread  
According to one embodiment, parallel processing optimization method for an apparatus configured to assign dynamically a part of some of basic modules, into which a program is divided and which...
8250395 Dynamic voltage and frequency scaling (DVFS) control for simultaneous multi-threading (SMT) processors  
A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the...
8230422 Assist thread for injecting cache memory in a microprocessor  
A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system...
8230410 Utilizing a bidding model in a microparallel processor architecture to allocate additional registers and execution units for short to intermediate stretches of code identified as opportunities for microparallelization  
An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities...
8225012 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8219996 Computer processor with fairness monitor  
A computer processor includes a fairness monitor for monitoring allocations of a processor resource to requestors. If unfairness is determined, a resource allocator is biased to offset said...
8214617 Apparatus and method of avoiding bank conflict in single-port multi-bank memory system  
Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second...
8200944 Method for instruction pipelining on irregular register files  
A method for pipelining instructions on a PAC processor includes determining a minimum initial interval, and grouping the instructions so that the operands of dependent instructions are assigned...