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7617494 Process for running programs with selectable instruction length processors and corresponding processor system  
The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the...
7603544 Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
7600221 Methods and apparatus of an architecture supporting execution of instructions in parallel  
A processing architecture supports executing instructions in parallel after identifying at least one level of dependency associated with a set of traces within a segment of code. Each trace...
7594078 D-cache miss prediction and scheduling  
A method and apparatus for D-cache miss prediction and scheduling is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one...
7571301 Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors  
A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure...
7509483 Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors  
A computing architecture and software techniques are described which modifies the basic sequential instruction fetching mechanism of a processor by separating a program's control flow from its...
7509482 Orderly processing ready entries from non-sequentially stored entries using arrival order matrix reordered upon removal of processed entries  
A memory device stores entries waiting to be processed. Row numbers of matrix information correspond to storage positions within the memory device, column numbers correspond to positions within the...
7475223 Fetch-side instruction dispatch group formation  
An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system....
7472257 Rerouting VLIW instructions to accommodate execution units deactivated upon detection by dispatch units of dedicated instruction alerting multiple successive removed NOPs  
Processor ( 100 ) has a plurality of registers ( 120 ) for storing instructions for execution by the plurality of execution units ( 160 ). The plurality of registers ( 120 ) are coupled to the...
7457938 Staggered execution stack for vector processing  
In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and...
7454597 Computer processing system employing an instruction schedule cache  
A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the...
7447887 Multithread processor  
To guarantee response time while strictly maintaining the priority specified by software, a processor ( 1 ) which is a multithread processor having a thread multiplexer ( 10 ), and an issue...
7447879 Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss  
A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at...
7441098 Conditional execution of instructions in a computer  
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation...
7437544 Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction  
A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an...
7430653 Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking  
A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource...
7430651 System and method for assigning tags to control instruction processing in a superscalar processor  
A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each...
7430643 Multiple contexts for efficient use of translation lookaside buffer  
The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table...
7421571 Apparatus and method for switching threads in multi-threading processors  
A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the...
7418575 Long instruction word processing with instruction extensions  
A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of...
7409530 Method and apparatus for compressing VLIW instruction and sharing subinstructions  
A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction...
7406586 Fetch and dispatch disassociation apparatus for multi-streaming processors  
A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions...
7401207 Apparatus and method for adjusting instruction thread priority in a multi-thread processor  
Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being...
7401204 Parallel Processor efficiently executing variable instruction word  
A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information....
7398374 Multi-cluster processor for processing instructions of one or more instruction threads  
The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the...
7395532 Process for running programs on processors and corresponding processor system  
Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to...
7395414 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions  
A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT...
7395413 System to dispatch several instructions on available hardware resources  
A processor (e.g., a co-processor) capable of executing instructions sequentially, comprises at least two functional hardware resources. When two instructions that are consecutive in program order...
7395408 Parallel execution processor and instruction assigning making use of group number in processing elements  
The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one...
7380107 Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss  
Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor...
7380104 Method and apparatus for back to back issue of dependent instructions in an out of order issue queue  
A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following...
7366884 Context switching system for a multi-thread execution pipeline loop and method of operation thereof  
A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context...
7360062 Method and apparatus for selecting an instruction thread for processing in a multi-thread processor  
The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor...
7353364 Apparatus and method for sharing a functional unit execution resource among a plurality of functional units  
An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to...
7343479 Method and apparatus for implementing two architectures in a chip  
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it...
7340591 Providing parallel operand functions using register file and extra path storage  
A number of architectural and implementation approaches are described for using extra path (Epath) storage that operate in conjunction with a compute register file to obtain increased instruction...
7337304 Processor for executing instruction control in accordance with dynamic pipeline scheduling and a method thereof  
When all of a plurality of instructions are symmetry instructions, a symmetry instruction issuing unit issues the symmetry instructions to a plurality of reservation stations provided for every...
7308563 Dual-target block register allocation  
A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined...
7278010 Instruction execution apparatus comprising a commit stack entry unit  
An instruction execution apparatus comprising a register storing a copy of contents of a maximum number of entries that are executable simultaneously in one cycle with the entry storing the oldest...
7269715 Instruction grouping history on fetch-side dispatch group formation  
An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching....
7269714 Inhibiting of a co-issuing instruction in a processor having different pipeline lengths  
A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to...
7266674 Programmable delayed dispatch in a multi-threaded pipeline  
Detecting a stall condition associated with processor instructions within one or more threads and generating a no-dispatch condition. The stall condition can be detected by hardware and/or software...
7257698 Instruction buffer and method of controlling the instruction buffer where buffer entries are issued in a predetermined order  
An instruction buffer of the present invention includes a sequence of instructions arranged in an order determined beforehand, and a buffer including entries arranged in a preselected order for...
7254689 Decompression of block-sorted data  
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
7254667 Data transfer between an external data source and a memory associated with a data processor  
A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with...
7240144 Arbitration of data transfer requests  
A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated...
7237095 Optimum power efficient shifting algorithm for schedulers  
A method and mechanism for managing shifts in a shifting queue. A reservation station in a processing device includes a queue of shifting entries. On a given cycle, zero, one, or two instructions...
7237094 Instruction group formation and mechanism for SMT dispatch  
A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the...
7234042 Identification bit at a predetermined instruction location that indicates whether the instruction is one or two independent operations and indicates the nature the operations executing in two processing channels  
An instruction set for a computer is described which includes instructions having a common predetermined bit length. That predetermined bit length can define a single operation or two independent...
7231510 Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof  
A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue...
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