Matches 401 - 442 out of 442 < 1 2 3 4 5 6 7 8 9
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5454115 Data driven type processor having data flow program divided into plurality of simultaneously executable program groups for an N:1 read-out to memory-access ratio  
A data driven type information processor includes a program storing unit, a junction unit, a paired data detecting unit, a branch unit and an operation processing unit. The program storing unit has...
5442760 Decoded instruction cache architecture with each instruction field in multiple-instruction cache line directly connected to specific functional unit  
A general purpose computer system is equipped with apparatus for enabling a processor to provide efficient execution of multiple instructions per clock cycle. The major feature is a decoded...
5442762 Instructing method and execution system for instructions including plural instruction codes  
An instructing method for specifying an instruction which is to be executed in an information processing apparatus, forms each of instruction words from at least an instruction code and an operand...
5434985 Simultaneous prediction of multiple branches for superscalar processing  
System and method for predicting a multiplicity of future branches simultaneously (parallel) from an executing program, to enable the simultaneous fetching of multiple disjoint program segments....
5430851 Apparatus for simultaneously scheduling instruction from plural instruction streams into plural instruction execution units  
Disclosed is an information processor comprising multiple instruction setup units which fetch and decode instructions as the first half of the procedure in instruction pipelines, each of the...
5414822 Method and apparatus for branch prediction using branch prediction table with improved branch prediction effectiveness  
The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch...
5410657 Method and system for high speed floating point exception enabled operation in a multiscalar processor system  
A method and system are disclosed for implementing floating point exception enabled operation without substantial performance degradation. In a multiscalar processor system, multiple instructions...
5408658 Self-scheduling parallel computer system and method  
An incremental method is described for distributing the instructions of an execution sequence among a plurality of processing elements for execution in parallel. The distribution is based upon...
5404469 Multi-threaded microprocessor architecture utilizing static interleaving  
A static interleaving technique solves the problem of resource contention in a very long instruction word multi-threaded microprocessor architecture. In the static interleaving technique, each...
5394558 Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM  
A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions...
5381533 Dynamic flow instruction cache memory organized around trace segments independent of virtual address line  
An improved cache and organization particularly suitable for superscalar architectures. The cache is organized around trace segments of running programs rather than an organization based on memory...
5377339 Computer for simultaneously executing instructions temporarily stored in a cache memory with a corresponding decision result  
A computer for simultaneously executing plural instructions decides the kind of operation and the possibility of simultaneous execution for the plural instructions as the instructions are read out...
5371864 Apparatus for concurrent multiple instruction decode in variable length instruction set computer  
A data processing apparatus for simultaneously reading out groups of two or more contiguous, variable length instructions from memory, and for decoding the group of variable length instructions in...
5355460 In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution  
A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions...
5337415 Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency  
A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the...
5333280 Parallel pipelined instruction processing system for very long instruction word  
A parallel pipelined instruction processing system for executing a plurality of instructions in parallel without no branch delay, comprises a instruction block fetch unit for fetching an...
5301341 Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions  
A mechanism is presented for detecting overflow in an interlock collapsing hardware apparatus that simultaneously executes two instructions. The overflow is determined as if the second instruction...
5287466 Method and apparatus for parallel loads equalizing utilizing instruction sorting by columns based on predicted instruction execution time  
A parallel processing system wherein the instruction field of each instruction is additionally provided with execution predict count information representative of the number of basic clocks...
H001291 Microprocessor in which multiple instructions are executed in one clock cycle by providing separate machine bus access to a register file for different types of instructions  
A microprocessor having a memory coprocessor (10) connected to a MEM interface (16) and a register coprocessor (12) connected to a REG interface (14). The REG interface (14) and MEM interface (16)...
5283874 Cross coupling mechanisms for simultaneously completing consecutive pipeline instructions even if they begin to process at the same microprocessor of the issue fee  
Apparatus and methods for expediting the completion of microprocessor instructions using a microprocessor pipelining system. Two or more dependent instructions processed through two or more...
5269007 RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register  
First and second instructions are simultaneously fetched from a memory to be respectively decoded by first and second instruction decoders. An instruction execution unit includes a register file,...
5251306 Apparatus for controlling execution of a program in a computing device  
An apparatus for controlling execution of a program of instructions in a computing device comprising an instruction fetching buffer-decoder for fetching the instructions in fetch batches and...
5241636 Method for parallel instruction execution in a computer  
A method for parallel instruction execution in a computer is described. If the computer is executing in the single-instruction mode and the computer encounters a first type of instruction with a...
5233694 Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneously  
The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A...
5214763 Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism  
A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their...
5197135 Memory management for scalable compound instruction set machines with in-memory compounding  
A digital computer system is described which is capable of processing 2 or more computer instructions in parallel and which has the capability of generating compounding tag information for those...
5185868 Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy  
An apparatus for use with a computing device for executing instructions in a logical sequence according to a control program, comprises an instruction buffer of FIFO construction serially connected...
5163139 Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions  
An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction...
5129067 Multiple instruction decoder for minimizing register port requirements  
A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers;...
5072364 Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel  
A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was...
5051885 Data processing system for concurrent dispatch of instructions to multiple functional units  
Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct...
4903196 Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor  
A method and apparatus for controlling access to its general purpose registers (GPRs) by a high end machine configuration including a plurality of execution units within a single CPU. The invention...
4807115 Instruction issuing mechanism for processors with multiple functional units  
An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple...
4803615 Microcode control of a parallel architecture microprocessor  
A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of...
4736288 Data processing device  
A data processing device which is equipped with a plurality of arithmetic units so that a plurality of instructions may be processed in parallel by the plural arithmetic units. The device includes...
4720779 Stored logic program scanner for a data processor having internal plural data and instruction streams  
A program scanner for a processor having multiple internal streams of instruction and data flow scans a sequence of incoming codes, and employs a plurality of rams to detect various types of...
4639886 Arithmetic system having pipeline structure arithmetic means  
An arithmetic system includes an arithmetic unit of a pipeline structure for executing arithmetic operations for instructions which require different arithmetic cycles. The arithmetic unit executes...
4574348 High speed digital signal processor architecture  
A data processor uses complex instructions and a sequence controller to cause first and second fields of such instructions to process data, respectively, by first and second ALUs, with a third...
4295193 Machine for multiple instruction execution  
A computing machine for concurrently executing instructions that have been compiled into a multi-instruction word comprised of a group of n instructions, where n is an integer. The group must not...
4151597 Microprogrammable control unit  
A microprogrammable control unit to be associated with a memory in which there have been pre-recorded two sequences of micro-instructions relating to two faces (digital systems) to be coupled and...
3771141 DATA PROCESSOR WITH PARALLEL OPERATIONS PER INSTRUCTION  
An electronic digital data processor particularly useful for performing tasks requiring substantial list processing computation in real (or neat real) time. The processor is organized in a manner...
3629853 DATA-PROCESSING ELEMENT  
A digital computer system having multiple memory units for storing information words representative of data and instructions, control means including means for extracting information words from the...
Matches 401 - 442 out of 442 < 1 2 3 4 5 6 7 8 9