Matches 201 - 250 out of 441 < 1 2 3 4 5 6 7 8 9 >
Match Document Document Title
6195744 Unified multi-function operation scheduler for out-of-order execution in a superscaler processor  
A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to...
6192461 Method and apparatus for facilitating multiple storage instruction completions in a superscalar processor during a single clock cycle  
One aspect of the invention relates to an apparatus for processing a store instruction on a superscalar processor that employs in-order completion of instructions, the processor having an...
6189087 Superscalar instruction decoder including an instruction queue  
A superscalar complex instruction set computer ("CISC") processor having a reduced instruction set computer ("RISC") superscalar core includes an instruction cache which identifies and marks raw...
6183141 Minimizing program code storage for performing regular and repetitive operations in a programmable processor  
The program memory comprises a first segment (MP1) containing a succession of program words including first base words (MMA) each having a size less than the sum of the respective sizes of the...
6182211 Conditional branch control method  
In order to effectively reduce branch hazards without a restriction to a structure of a pipeline, the contents of instructions and the like during control of conditional branching in an information...
6161172 Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor  
A method of instruction dispatch is provided in which a directly-decoded instruction and a microcode instruction are concurrently dispatched ("packed"). The instruction which is second in program...
6157996 Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space  
A processor for executing computer instructions including, in one embodiment, a machine specific register (MSR) which includes a predicated execution field and an instruction decoder. The decoder...
6157964 Method for specifying concurrent execution of a string of I/O command blocks in a chain structure  
An I/O command block, that is stored in a memory, includes information for connecting the I/O command block to other I/O command blocks in a chain structure. The I/O command block chain structure...
6154792 Method and computer program product for paging control using a reference structure including a reference bitmap  
A method and computer program product are provided for paging control using a reference structure in a computer system. The reference structure is scanned to identify a next selected entry for an...
6148393 Apparatus for generating a valid mask  
A valid mask generator comprising a series of mask generation blocks. Each block generates a predetermined number of valid mask bits given a predetermined number of start pointer bits and end bits,...
6148391 System for simultaneously accessing one or more stack elements by multiple functional units using real stack addresses  
Embodiments of the present invention provide a stack renaming method and apparatus for stack based processors. Using principles of the present invention, a stack can be accessed simultaneously by...
6141675 Method and apparatus for custom operations  
Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time...
6134651 Reorder buffer employed in a microprocessor to store instruction results having a plurality of entries predetermined to correspond to a plurality of functional units  
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently...
6122727 Symmetrical instructions queue for high clock frequency scheduling  
An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that...
6122722 VLIW processor with less instruction issue slots than functional units  
Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register.
6115807 Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued  
The invention, in one embodiment, is a static instruction decoder including a plurality of instruction inputs, a circular instruction queue, and an instruction rotator. The circular instruction...
6112296 Floating point stack manipulation using a register map and speculative top of stack values  
A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of...
6108768 Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system  
An execution unit that executes multiple instructions as a single instruction group during a single processing cycle is provided. The execution unit handles problem causing instruction groups by...
6105127 Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream  
A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of...
6105128 Method and apparatus for dispatching instructions to execution units in waves  
A first embodiment provides an apparatus including a first execution unit capable of executing a first type and a second type of ready instruction, a second execution unit capable of executing the...
6101596 Information processor for performing processing without register conflicts  
An information processor is capable of eliminating register conflict in short and long latency processes and for attaining high-speed pipeline processing through efficient use of registers. The...
6098165 Fetching and handling a bundle of instructions comprising instructions and non-complex instructions  
In a processor that executes complex instructions which are expanded into microinstructions prior to execution, non-complex instruction execution is optimized by providing a by-passable helper...
6098166 Speculative issue of instructions under a load miss shadow  
A technique for speculatively issuing instructions using an out-of-order processor. A cache miss by a load instruction results in either a reissue of all subsequently issued instructions for an...
6092183 Data processor for processing a complex instruction by dividing it into executing units  
A compact and small compensating-electric-power data processor is realized by dividing a plurality of calculations to be carried out by a complex instruction into a number of executing units to be...
6092175 Shared register storage mechanisms for multithreaded computer systems with out-of-order execution  
A method and organization for implementing the registers required in a computer system supporting multithreading and dynamic out-of-order execution. Multithreaded computer systems are those in...
6092184 Parallel processing of pipelined instructions having register dependencies  
A method of processing instructions having register dependencies in a pipelined superscalar processor comprises the steps of fetching operands specified by a first instruction during a first...
6085305 Apparatus for precise architectural update in an out-of-order processor  
A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results...
6085311 Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch  
A microprocessor includes an instruction alignment unit for locating instructions and conveying the located instructions to a set of decode units. The instruction alignment unit includes dual...
6081884 Embedding two different instruction sets within a single long instruction word using predecode bits  
A microprocessor optimized to execute two instruction sets in a long instruction word (LIW) format. One instruction set may have variable length instructions. The microprocessor has an alignment...
6076154 VLIW processor has different functional units operating on commands of different widths  
A VLIW processor has first and second functional units for executing first and second commands in a first instruction word. The first and second commands comprise a first field and a second field,...
6073231 Pipelined processor with microcontrol of register translation hardware  
A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, with one or more of said instructions referencing a set of logical...
6065105 Dependency matrix  
In a microprocessor, an instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the...
6065110 Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue  
A method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue are disclosed. The processor capable of out-of-order instruction issue includes an...
6061777 Apparatus and method for reducing the number of rename registers required in the operation of a processor  
One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently...
6055629 Predicting for all branch instructions in a bunch based on history register updated once for all of any taken branches in a bunch  
A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The...
6052775 Method for non-intrusive cache fills and handling of load misses  
A method for operating a processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay...
6049864 Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor  
A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating...
6047368 Processor architecture including grouping circuit  
A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the...
6046741 Visual command sequence desktop agent  
User commands and command parameters in a graphical user interface are logged in a command log. Repeating patterns of commands and command parameters are automatically detected. This detection is...
6047367 Microprocessor with improved out of order support  
A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential...
6044450 Processor for VLIW instruction  
Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the...
6044451 VLIW processor with write control unit for allowing less write buses than functional units  
Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register.
6041405 Instruction length prediction using an instruction length pattern detector  
A microprocessor configured to predict the length of variable length instructions for decoding purposes by detecting patterns of instruction lengths that have been previously decoded. The...
6038584 Synchronized MIMD multi-processing system and method of operation  
There is disclosed a multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication...
6038657 Scan chains for out-of-order load/store execution control  
Scan logic which tracks the relative age of stores with respect to a particular load (or of loads with respect to a particular store) allows at processor to hold younger stores until the completion...
6035389 Scheduling instructions with different latencies  
An apparatus includes a clock to produce pulses and an electronic hardware structure having a plurality of rows and one or more ports. Each row is adapted to record a separate latency vector...
6032244 Multiple issue static speculative instruction scheduling with path tag and precise interrupt handling  
The present invention features a computer with a mechanism for implementing precise interrupts for statically speculated instructions. One or more assumptions are generated, and all instructions in...
6032251 Computer system including a microprocessor having a reorder buffer employing last in buffer and last in line indications  
A computer system including a microprocessor employing a reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication...
6032252 Apparatus and method for efficient loop control in a superscalar microprocessor  
A superscalar microprocessor implements a repeated string instruction by putting the microcode unit in a continuous loop. The microcode sequence that implements the repeated string operation...
6029242 Data processing system using a shared register bank and a plurality of processors  
A system and method is provided for use in register-based CPUs for simultaneously processing data in a series of CPU register banks while concurrently loading and unloading data into additional...
Matches 201 - 250 out of 441 < 1 2 3 4 5 6 7 8 9 >