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6418527 Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods  
A system for instructing a data processor, the system including an instruction root having an operation selection field for selecting an operation to be performed by said data processor and an...
6412061 Dynamic pipelines with reusable logic elements controlled by a set of multiplexers for pipeline stage selection  
A method of dynamically adjusting a multiple stage pipeline to execute one of a set of instructions, wherein each stage has a latency and performs a selected data operation. An instruction to be...
6408377 Dynamic allocation of resources in multiple microprocessor pipelines  
A microprocessor having M parallel pipelines and N arithmetic logic units, where N is less than M. A single instruction fetch stage fetches multi-stage instructions, and a single instruction...
6405267 Command reordering for out of order bus transfer  
A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory...
6397319 Process for executing highly efficient VLIW  
A 32-bit instruction 50 is composed of a 4-bit format field 51 , a 4-bit operation field 52 , and two 12-bit operation fields 59 and 60 . The 4-bit operation field 52 can only include (1)...
6393549 Instruction alignment unit for routing variable byte-length instructions  
An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a...
6385719 Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor  
A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher....
6381689 Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction  
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently...
6378061 Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit  
An instruction decoder that issues new instructions by driving a machine bus ( 110 ) with the correct information during each clock cycle. This information is either extracted from the current...
6370637 Optimized allocation of multi-pipeline executable and specific pipeline executable instructions to execution pipelines based on criteria  
A microprocessor with a floating point unit configured to efficiently allocate multi-pipeline executable instructions is disclosed. Multi-pipeline executable instructions are instructions that are...
6367076 Compiling method and memory storing the program code  
A compiling method, for compiling a source program into an object program for a CPU having multiple functional units that allow for concurrent operations and supporting predicated execution, for...
6363441 TIMING CONTROLLER HAVING DEPENDENCY MEMORY, SELECTION SERIALIZATION COMPONENT AND REORDERING COMPONENT FOR MAINTAINING TIME DEPENDENCIES IN CONVERSIONS BETWEEN SEQUENTIAL AND PARALLEL OPERATIONS USING STAGING MEMORY  
An electronic system and method that maintains time dependencies and ordering constraints in an electronic system. A timing controller utilizes a representative bit to track timing dependencies...
6360313 Instruction cache associative crossbar switch  
A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied...
6353881 Supporting space-time dimensional program execution by selectively versioning memory updates  
A system is provided that facilitates space and time dimensional execution of computer programs through selective versioning of memory elements located in a system heap. The system includes a head...
6353880 Four stage pipeline processing for a microcontroller  
A system and method for efficiently processing instructions in a pipeline architecture for a microcontroller and maintaining a fixed instruction execution per clock cycle rate is disclosed. The...
6351807 Data processing system utilizing multiple resister loading for fast domain switching  
A processor ( 40 ) in a data processing system simultaneously loads multiple registers ( 60 ) with a single value for fast domain switching. A domain switch instruction asserts a register block...
6351802 Method and apparatus for constructing a pre-scheduled instruction cache  
A method of scheduling instructions in a computer processor. The method comprises fetching instructions to create an in-order instruction buffer, and scheduling instruction from the instruction...
6351806 Risc processor using register codes for expanded instruction set  
A RISC processor using a fixed length standard instruction word (32-bit) consisting of a fixed-length (6-bit) operation code and two register fields, uses one of the register fields to give certain...
6345355 Method and apparatus for distributing commands to a plurality of circuit blocks  
A command memory stores commands in memory words. Each command has a label field and an action field. The commands are consolidated to reduce the amount of information stored in the command memory....
6341343 Parallel processing instructions routed through plural differing capacity units of operand address generators coupled to multi-ported memory and ALUs  
Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions...
6330657 Pairing of micro instructions in the instruction queue  
An apparatus and method are presented for increasing the throughput within a single-channel of a pipeline microprocessor. Back-to-back pairs of micro instructions are evaluated to determine if they...
6324639 Instruction converting apparatus using parallel execution code  
A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is...
6324640 System and method for dispatching groups of instructions using pipelined register renaming  
Within a superscalar processor, multiple groups of instructions are dispatched simultaneously to a plurality of execution units. A renaming mechanism is utilized to permit out-of-order execution of...
6314471 Techniques for an interrupt free operating system  
A method and system in a multithreaded processor for processing events without interrupt notifications. In one aspect of the present invention, an operating system creates a thread to execute on a...
6311266 Instruction look-ahead system and hardware  
A method and system for executing instructions in a computer. Each instruction has a look-ahead code indicating the number of instructions after which may be executed before its own execution is...
6308260 Mechanism for self-initiated instruction issuing and method therefor  
An apparatus and method for self-initiated instruction issuing are implemented. In a central processing unit (CPU) having a pipelined architecture, instructions are queued for issuing to the...
6308259 Instruction queue evaluating dependency vector in portions during different clock phases  
An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that...
6308254 Processing instructions of an instruction set architecture by executing hierarchically organized snippets of atomic units of primitive operations  
A processor is provided with a datapath and control logic to control the datapath to selectively execute a number of hierarchically organized primitive operations to effectuate execution of user...
6304954 Executing multiple instructions in multi-pipelined processor by dynamically switching memory ports of fewer number than the pipeline  
Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions...
6304959 Simplified method to generate BTAGs in a decode unit of a processing system  
A method and system for assigning unique branch tag (BTAG) values in a decode unit in a processing system are disclosed. The method and system comprise providing at least one BTAG value and...
6304953 Computer processor with instruction-specific schedulers  
One embodiment of the present invention is a computer processor that includes a first scheduler adapted to dispatch a first type of computer instructions, and a second scheduler coupled to the...
6292882 Method and apparatus for filtering valid information for downstream processing  
In one aspect, the invention includes an apparatus for filtering instructions within a digital system that eliminates the need to physically switch the valid instructions onto consecutive data...
6292845 Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively  
An instruction fetching unit is described for loading instructions from a memory processed by a data processing device. The instruction code can be of at least two different lengths, and each...
6292884 Reorder buffer employing last in line indication  
A reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction...
6282635 Method and apparatus for controlling an instruction pipeline in a data processing system  
An address translation memory stores a plurality of virtual address tags. The virtual address tags typically designate a portion of the virtual address space corresponding to a page of data stored...
6279101 Instruction decoder/dispatch  
A super-scalar microprocessor performs operations upon a plurality of instructions at each of its fetch, decode, execute, and write-back stages. To support such operations, the super-scalar...
6272625 Apparatus and method for processing events in a digital versatile disc (DVD) system using system threads and separate dormant/awake counter threads and clock driven semaphores  
A multi-threaded digital versatile disc system which is controlled by a system thread includes an independent counter thread for controlling the counter parameters. Only the counter thread (and not...
6266765 Computer architecture capable of execution of general purpose multiple instructions  
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
6266745 Method and system in a distributed shared-memory data processing system for determining utilization of nodes by each executed thread  
A method and system in a distributed shared-memory data processing system are disclosed for determining a utilization of each of a plurality of coupled processing nodes by one of a plurality of...
6260133 Processor having operating instruction which uses operation units in different pipelines simultaneously  
An instruction fetch unit 10 issues a normal ALU operating instruction or a wide ALU operating instruction using two operating units to a first pipeline 14. The instruction fetch unit 10 also...
6256726 Data processor for the parallel processing of a plurality of instructions  
The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A...
6256730 Apparatus and method of processing counter parameters in a digital versatile disc system  
A multi-threaded digital versatile disc system which is controlled by a system thread includes an independent counter thread for controlling the counter parameters. Only the counter thread (and not...
6247124 Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions  
A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction...
6247120 Instruction buffer for issuing instruction sets to an instruction decoder  
An instruction buffer includes a shift register having M storage elements to store instructions before the instructions are issued to an instruction decoder. The instruction buffer also includes...
6237082 Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received  
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently...
6237077 Instruction template for efficient processing clustered branch instructions  
A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions...
6237086 1 Method to prevent pipeline stalls in superscalar stack based computing systems  
An execution unit for a stack based computing system that can combine instructions into instruction groups for concurrent execution is provided. In accordance with one embodiment, the instructions...
6233492 Process control system and method for transferring process data therefor  
A process control system includes a plurality of machine controllers for individually controlling a plurality of process chambers and a main controller for controlling the machine controllers. Each...
6219780 Circuit arrangement and method of dispatching instructions to multiple execution units  
A data processing system, circuit arrangement, integrated circuit device, program product, and method dispatch multiple copies of a producer instruction to multiple execution units in a processor...
6209081 Method and system for nonsequential instruction dispatch and execution in a superscalar processor system  
A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of...
Matches 151 - 200 out of 441 < 1 2 3 4 5 6 7 8 9 >