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7620803 Data processing device and electronic equipment using pipeline control  
A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline...
7613904 Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler  
A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a...
7603544 Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
7594097 Microprocessor output ports and control of instructions provided therefrom  
A method and apparatus are provided for controlling instructions provided by a microprocessor output port to other execution units. A microprocessor pipeline of instructions is provided for each...
7590824 Mixed superscalar and VLIW instruction issuing and processing method and system  
Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal...
7587717 Dynamic master/slave configuration for multiple expansion modules  
A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes...
7562206 Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitions  
Microarchitecture policies and structures to predict execution clusters and facilitate inter-cluster communication are disclosed. In disclosed embodiments, sequentially ordered instructions are...
7552434 Method of performing kernel task upon initial execution of process at user level  
An embodiment of a method of performing a kernel level task upon initial execution of a child process at a user level begins with setting an instruction pointer for an initial child process...
7552313 VLIW digital signal processor for achieving improved binary translation  
A VLIW digital signal processor is composed of a program memory including first to n-th banks, first to n-th address counters, a fetch block, and an instruction executing section. The first to n-th...
7533248 Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor  
A multithreaded processor including a shared functional unit. In one embodiment, the multithreaded processor includes a functional unit coupled to a multithreaded instruction source that may...
7523297 Shadow scan decoder  
Methods and circuitry for processing a shadow scan instruction in a multi-threaded microprocessing environment include a bit sequence having a thread identifier, core identifiers and a shadow scan...
7523295 Processor and method of grouping and executing dependent instructions in a packet  
An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a...
7509483 Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors  
A computing architecture and software techniques are described which modifies the basic sequential instruction fetching mechanism of a processor by separating a program's control flow from its...
7509482 Orderly processing ready entries from non-sequentially stored entries using arrival order matrix reordered upon removal of processed entries  
A memory device stores entries waiting to be processed. Row numbers of matrix information correspond to storage positions within the memory device, column numbers correspond to positions within the...
7502914 Transitive suppression of instruction replay  
In one embodiment, a processor comprises one or more execution resources configured to execute instruction operations and a scheduler coupled to the execution resources. The scheduler is configured...
7502913 Switch prefetch in a multicore computer chip  
Systems and methods for switch prefetch in multicore computer chips can allow a programmer to tailor operations of a computer program to available data. Control-flow decisions can be made by the...
7502912 Method and apparatus for rescheduling operations in a processor  
A method and apparatus for rescheduling operations in a processor. More particularly, the present invention relates to optimally using a scheduler resource in a processor by analyzing, predicting,...
7500086 Start transactional execution (STE) instruction to support transactional program execution  
One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally....
7496899 Preventing loss of traced information in a data processing apparatus  
Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided. The data...
7496490 Multi-core-model simulation method, multi-core model simulator, and computer product  
Core model processing of a processor model PE1 and a processor model PE2 is serialized. Therefore, processing time for the inter-core-model communication is required between the core model...
7493475 Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address  
An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to...
7493469 Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium  
From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the...
7490224 Time-of-life counter design for handling instruction flushes from a queue  
Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the...
7490219 Counter counts valid requests based on a judgment in a system having a plurality of pipeline processors  
In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register...
7487335 Method and apparatus for accessing registers during deferred execution  
One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order....
7480771 Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged  
We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated,...
7478225 Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor  
An apparatus and method to support pipelining of variable-latency instructions in a multithreaded processor. In one embodiment, a processor may include instruction fetch logic configured to issue a...
7475225 Method and apparatus for microarchitecture partitioning of execution clusters  
Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are...
7464253 Tracking multiple dependent instructions with instruction queue pointer mapping table linked to a multiple wakeup table by a pointer  
A method and apparatus for improving the operation of an out-of order computer processor by utilizing and managing instruction wakeup using pointers with an instruction queue payload random-access...
7444498 Load lookahead prefetch for microprocessors  
The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the...
7437538 Apparatus and method for reducing execution latency of floating point operations having special case operands  
An apparatus and method for floating-point special case handling. In one embodiment, a processor may include a first execution unit configured to execute a longer-latency floating-point...
7418576 Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operations  
A graphics processor buffers vertex thread and pixel threads. The different types of threads issue instructions corresponding to different sets of operations. A plurality of different types of...
7409530 Method and apparatus for compressing VLIW instruction and sharing subinstructions  
A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction...
7401206 Apparatus and method for fine-grained multithreading in a multipipelined processor core  
An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given...
7395082 Method and system for handling events in an application framework for a wireless device  
Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI...
7392367 Command ordering among commands in multiple queues using hold-off vector generated from in-use vector and queue dependency scorecard  
A method, apparatus, system, and signal-bearing medium that in various embodiments determine whether to execute a command in a queue or whether to wait until another command or commands completed....
7392366 Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches  
A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream...
7383425 Massively reduced instruction set processor  
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to...
7380105 Prediction based instruction steering to wide or narrow integer cluster and narrow address generation  
A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus...
7380104 Method and apparatus for back to back issue of dependent instructions in an out of order issue queue  
A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following...
7376954 Mechanisms for assuring quality of service for programs executing on a multithreaded processor  
A mechanism for assuring quality of service for a context in a digital processor has a first scheduling register dedicated to the context, the register having N out of M bits set, and a first...
7370176 System and method for high frequency stall design  
A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction...
7366878 Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching  
A processor buffers asynchronous threads. Current instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one math operation...
7366877 Speculative instruction issue in a simultaneously multithreaded processor  
A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers...
7363625 Method for changing a thread priority in a simultaneous multithread processor  
An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in...
7363467 Dependence-chain processing using trace descriptors having dependency descriptors  
An apparatus and method for a processor microarchitecture that quickly and efficiently takes large steps through program segments without fetching all intervening instructions. The...
7360064 Thread interleaving in a multithreaded embedded processor  
The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization...
7350056 Method and apparatus for issuing instructions from an issue queue in an information handling system  
An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some...
7343475 Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction  
A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format...
7343474 Minimal address state in a fine grain multithreaded processor  
In one embodiment, a processor comprises a plurality of pipeline stages and a first circuit operable at a first pipeline stage of the plurality of pipeline stages. The first circuit is configured...
Matches 1 - 50 out of 294 1 2 3 4 5 6 >