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7590832 Information processing device, compressed program producing method, and information processing system  
An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the...
7509481 Patchable and/or programmable pre-decode  
Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode...
7487334 Branch encoding before instruction cache write  
Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes...
7454597 Computer processing system employing an instruction schedule cache  
A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the...
7447876 System and method for handling load and/or store operations in a superscalar microprocessor  
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
7441104 Parallel subword instructions with distributed results  
The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify...
7415638 Pre-decode error handling via branch correction  
In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding...
7395414 Dynamic recalculation of resource vector at issue queue for steering of dependent instructions  
A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT...
7395412 Apparatus and method for extending data modes in a microprocessor  
An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instructions in...
7376815 Methods and apparatus to insure correct predecode  
Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One...
7366874 Apparatus and method for dispatching very long instruction word having variable length  
Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer...
7360060 Using IMPDEP2 for system commands related to Java accelerator hardware  
A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder...
7356673 System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form  
A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second...
7346760 Data processing apparatus of high speed process using memory of low speed and low power consumption  
When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout...
7340589 Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction  
The data processing device and electronic equipment of the present invention perform pipeline control and include a fetch circuit which fetches instruction codes of a plurality of instructions in...
7334111 Method and related device for use in decoding executable code  
The invention provides for a method and related device and control program for use in decoding executable code in a processing system, for example run-time operating system, including bit-shuffling...
7328328 Non-temporal memory reference control mechanism  
An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and...
7321963 System and method for storing immediate data  
An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is...
7305676 Communication device configured for real time processing of user data to be transmitted  
A communication device is provided which has a programmable multichannel signal processor for real time processing of user data, which are to be transmitted, within the framework of a plurality of...
7305542 Instruction length decoder  
Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four...
7290081 Apparatus and method for implementing a ROM patch using a lockable cache  
A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first...
7266674 Programmable delayed dispatch in a multi-threaded pipeline  
Detecting a stall condition associated with processor instructions within one or more threads and generating a no-dispatch condition. The stall condition can be detected by hardware and/or software...
7254697 Method and apparatus for dynamic modification of microprocessor instruction group at dispatch  
Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of...
7246218 Systems for increasing register addressing space in instruction-width limited processors  
A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file,...
7237094 Instruction group formation and mechanism for SMT dispatch  
A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the...
7210139 Processor cluster architecture and associated parallel processing methods  
A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program...
7200738 Reducing data hazards in pipelined processors to provide high processor utilization  
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on...
7197653 Microcontroller for fetching and decoding a frequency control signal together with an operation code  
A microcontroller is realized that is capable of eliminating the time lag required for changing the frequency during operation and of reducing power consumption by accurately and rapidly performing...
7194602 Data processor  
A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a...
7178046 Halting clock signals to input and result latches in processing path upon fetching of instruction not supported  
A microprocessor includes a first cache memory, a first instruction fetch unit, a first instruction decoder, a first processing unit and a first latch that holds a control signal outputted from the...
7174469 Processor power and energy management  
Methods and systems for managing power and energy expenditures in cores of a processor to balance performance with power and energy dissipation are disclosed. Embodiments may include pre-decoder(s)...
7114057 System and method for storing immediate data  
An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is...
7065413 Method for producing software for controlling mechanisms and technical systems  
In a method for controlling mechanisms or technical systems, the mechanisms or technical systems to be controlled are stored in a controller with their states, and with associated signal formers of...
7065215 Microprocessor with program and data protection function under multi-task environment  
In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the...
7007154 Method and apparatus for interfacing a processor to a coprocessor  
A processor ( 12 ) to coprocessor ( 14 ) interface supporting multiple coprocessors ( 14, 16 ) utilizes compiler generatable software type function call and return, instruction execute, and...
7003649 Control forwarding in a pipeline digital processor  
A data processor includes at least one instruction pipeline for executing an instruction stream having branch instructions. The choices of a branch instruction, the next inline instruction or a...
6988184 Dyadic DSP instruction predecode signal selective multiplexing data from input buses to first and second plurality of functional blocks to execute main and sub operations  
Methods of performing dyadic digital signal processing (DSP) instructions. In one embodiment of the invention, the method includes fetching a dyadic DSP instruction having a main operation and a...
6978233 Method for emulating multi-processor environment  
A method of and an apparatus for performing efficient software emulation of a multi-processor target computer by a host computer. The software technique permits multiple processors to be emulated...
6952754 Predecode apparatus, systems, and methods  
An apparatus and a system may include a modal property indicator and an access module to receive the modal property indicator and to access a selected location based on a condition of the modal...
6948053 Efficiently calculating a branch target address  
A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n−1 lower order bits of the branch target address may be pre-calculated and stored...
6918031 Setting condition values in a computer  
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation...
6883087 Processing of binary data for compression  
Binary data is processed and organized by determining patterns specific for the binary data in a software package. Code sections may be split from an instruction according to the code section type...
6880074 In-line code suppression  
Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes)...
6877087 Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving  
A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point...
6874078 Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit  
A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to...
6862676 Superscalar processor having content addressable memory structures for determining dependencies  
A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an...
6857061 Method and apparatus for obtaining a scalar value directly from a vector register  
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
6832307 Instruction fetch buffer stack fold decoder for generating foldable instruction status information  
A plurality of fold decoders are each coupled to a different set of successive entries within an instruction fetch buffer stack and check the contents of the successive entries for a variable...
6832194 Audio recognition peripheral system  
The present invention includes a novel audio recognition peripheral system and method. The audio recognition peripheral system comprises an audio recognition peripheral a programmable processor...
6820223 Processor, compiling apparatus, and compile program recorded on a recording medium  
Each of registers R 0 to R 31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the...
Matches 1 - 50 out of 243 1 2 3 4 5 >