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RE41012 |
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the...
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7617388 |
Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at...
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7533250 |
Automatic operand load, modify and store
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode...
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7519799 |
Apparatus having a micro-instruction queue, a micro-instruction pointer programmable logic array and a micro-operation read only memory and method for use thereof
Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single...
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7506322 |
System and method of utilizing a hardware component to execute an interpretive language
A system and method of executing an interpretive language in a system having a processing component with native software processes and a memory component. A hardware component is coupled with the...
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7502725 |
Method, system and computer program product for register management in a simulation environment
A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed...
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7500085 |
Identifying code for compilation
A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch...
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7398376 |
Instructions for ordering execution in pipelined processes
Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory...
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7398372 |
Fusing load and alu operations
Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a...
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7321963 |
System and method for storing immediate data
An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is...
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7290120 |
Microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer
A microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer is disclosed. The microprocessor...
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7290081 |
Apparatus and method for implementing a ROM patch using a lockable cache
A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first...
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7281121 |
Pipeline processing device and interrupt processing method
At an MA stage, data, such as a header address of an interrupt processing routine, is loaded via a data bus and immediately supplied to a program counter via multiplexers without the intervention...
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7213126 |
Method and processor including logic for storing traces within a trace cache
A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be...
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7191314 |
Reconfigurable CPU with second FSM control unit executing modifiable instructions
A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set...
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7162621 |
Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at...
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7143265 |
Computer program product memory access system
A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred...
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7139897 |
Computer instruction dispatch
Circuit arrangement and method for dispatching computer instructions. In a processor having a plurality of types of execution units, the computer instructions are grouped in bundles, and each...
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7114057 |
System and method for storing immediate data
An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is...
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7111148 |
Method and apparatus for compressing relative addresses
A method and apparatus for compressing relative addresses and for storage of compressed relative addresses. A relative virtual address is computed in a particular stage of a processor pipeline and...
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7107439 |
System and method of controlling software decompression through exceptions
When processor instructions are required for execution, a misaligned address is sent to the processor. The misaligned instruction address causes a computer processor exception. The computer system...
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7107434 |
System, method and apparatus for allocating hardware resources using pseudorandom sequences
The present invention provides a system, method and apparatus for allocating resources by assigning resource identifiers to processor resources using at least a portion of a pseudorandom sequence....
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6957322 |
Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion
A microcode instruction unit for a processor may include a microcode memory having entries for storing microcode instructions. A decoder for the microcode memory may decode microcode addresses to...
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6957321 |
Instruction set extension using operand bearing NOP instructions
Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second...
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6957319 |
Integrated circuit with multiple microcode ROMs
Integrated circuits having multiple independently accessible microcode ROMs. An integrated circuit may include a microcode unit and a plurality of microcode ROMs fabricated within the same...
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6877069 |
History-based carry predictor for data cache address generation
An address translation logic and method for generating an instruction's operand address. The address generation logic includes an address generation circuit having adders that perform partial sum...
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6820191 |
Apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor
An apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor is provided. The method includes...
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6817015 |
Microcontroller with modifiable program
A microcontroller has a nonvolatile memory that originally stores program code and has free space. When part of the program code needs to be modified, that part is disabled, and modified program...
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6789186 |
Method and apparatus to reduce penalty of microcode lookup
A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The...
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6789185 |
Instruction control apparatus and method using micro program
A control reservation station stores the control information of a micro program to control one or more flows of an instruction process and controls each flow using the control information. A data...
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6779102 |
Data processor capable of executing an instruction that makes a cache memory ineffective
A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the...
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6742107 |
Dynamically configured processing of composite stream input data using next conversion determining state transition table searched by converted input data
A table storing a state transition rule is arranged in a memory. By referencing the table based on input data, the process to be performed for the input data is determined and executed....
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6732258 |
IP relative addressing
A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an...
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6654875 |
Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator
Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is...
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6647488 |
Processor
A processor is adapted to support a complex instruction set without making major modifications to the existing hardware but by adding just a few controls and thereby emulating instructions in...
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6618803 |
System and method for finding and validating the most recent advance load for a given checkload
The present invention discloses a system and method for simultaneously identifying a most recent advanced load instruction employing a particular register and determining whether the instruction...
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6611909 |
Method and apparatus for dynamically translating program instructions to microcode instructions
In a computer system the instruction decoding unit for translating program instructions to microcode instructions operates dynamically. Thus the unit receives state signals indicating the state of...
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6542981 |
Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode
A method and apparatus for invoking microcode instructions resident on a processor by executing a special RISC instruction on the processor such that special functions are provided. In one...
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6463521 |
Opcode numbering for meta-data encoding
A method for including opcode information in an opcode includes numbering the opcode such that a property of the opcode is represented by at least one bit of the opcode. According to one aspect,...
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6457117 |
Processor configured to predecode relative control transfer instructions and replace displacements therein with a target address
The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement...
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6446190 |
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the...
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6442675 |
Compressed string and multiple generation engine
A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the operations contained in...
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6442672 |
Method for dynamic allocation and efficient sharing of functional unit datapaths
The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning...
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6438680 |
Microprocessor
When a decision circuit ( 217 ) incorporated in a control circuit ( 21 ) in an instruction decode unit ( 2 ) in a microprocessor ( 1 ) decides that an integer operation unit ( 4 ) can not execute a...
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6412062 |
Injection control mechanism for external events
The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified....
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6397319 |
Process for executing highly efficient VLIW
A 32-bit instruction 50 is composed of a 4-bit format field 51 , a 4-bit operation field 52 , and two 12-bit operation fields 59 and 60 . The 4-bit operation field 52 can only include (1)...
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6378062 |
Method and apparatus for performing a store operation
The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by...
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6367003 |
Digital signal processor having enhanced utilization of multiply accumulate (MAC) stage and method
A digital signal processor (DSP) architecture which allows the DSP Multiply-Accumulator (MAC) to be used for special fixed functions during those times when the programmable portions of the DSP are...
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6367002 |
Apparatus and method for fetching instructions for a program-controlled unit
An apparatus and a method are distinguished in that an instruction queue is provided which is configured such that when instruction data are written into the instruction queue and/or when...
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6360297 |
System bus read address operations with data ordering preference hint bits for vertical caches
A method for preferentially ordering the retrieval of data from a cache line of a cache within a vertical cache configuration. The method includes the steps of first encoding a set of bits with a...
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