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7594098 |
Processes and devices for compression and decompression of executable code by a microprocessor with RISC architecture and related system
An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into...
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7587535 |
Data transfer control device including endian conversion circuit with data realignment
When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the...
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7581084 |
Method and apparatus for efficient loading and storing of vectors
A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location...
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7581083 |
Operation processing device, system and method having register-to-register addressing
As shown in FIG. 1, an operation-processing device of the present invention comprises a register array ( 11 ) having plural registers for holding an arbitrary value based on a write address Aw...
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RE40883 |
Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision
A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A...
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7565510 |
Microprocessor with a register selectively storing unaligned load instructions and control method thereof
A load/store unit includes a Top register for storing a value retained before loading to a load destination register and a saved register capable of storing data retained to the Top register. When...
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7543134 |
Apparatus and method for extending a microprocessor instruction set
An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an...
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7529912 |
Apparatus and method for instruction-level specification of floating point format
Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an...
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7526633 |
Method and system for encoding variable length packets with variable instruction sizes
Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction...
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7523294 |
Maintaining original per-block number of instructions by inserting NOPs among compressed instructions in compressed block of length compressed by predetermined ratio
The present invention discloses a method for compressing instruction codes. This method comprises: compressing an instruction block including a plurality of instructions according to...
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7523230 |
Device and method for maximizing performance on a memory interface with a variable number of channels
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of...
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7502911 |
Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length
A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions...
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7493470 |
Processor apparatus and methods optimized for control applications
Apparatus and methods for real-time control using a data processor. In one aspect, the invention comprises an improved processor having one or more extension instructions (and associated supporting...
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7490118 |
Expanding instruction set using alternate error byte
Expanding the capacity of a fixed digital field using a unique number calculated from the digital field, such as an error code. Expansion is possible by calculating a new error code using a...
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7454594 |
Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements
A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and...
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7447871 |
Data access program instruction encoding
A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit...
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7424597 |
Variable reordering (Mux) instructions for parallel table lookups from registers
Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an...
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RE40498 |
Variable address length compiler and processor improved in address management
The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit...
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7421566 |
Implementing instruction set architectures with non-contiguous register file specifiers
There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code...
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7376814 |
Method for forming variable length instructions in a processing system
Variable length instructions are formed for execution in a processing system. Each instruction includes a parameter portion having one or more of predetermined types of parameters and an opcode...
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7373483 |
Mechanism for extending the number of registers in a microprocessor
An apparatus and method are provided, for accessing extended registers within a microprocessor. The apparatus includes translation logic and extended register logic. The translation logic...
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7366876 |
Efficient emulation instruction dispatch based on instruction width
In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine...
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7360061 |
Program instruction decompression and compression techniques
A data processing system including an instruction cache 8 and an instruction decompression circuit 10 between the instruction cache 8 and a compressed instruction data memory 12 . The...
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7353368 |
Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support
A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking...
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7343473 |
System and method for translating non-native instructions to native instructions for processing on a host processor
A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning...
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7343471 |
Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions
Instructions of a program are stored in compressed form in a program memory ( 12 ). In a processor which executes the instructions, a program counter ( 50 ) identifies a position in the program...
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7340590 |
Handling register dependencies between instructions specifying different width registers
The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If...
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7340588 |
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code...
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7328328 |
Non-temporal memory reference control mechanism
An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and...
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7305542 |
Instruction length decoder
Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four...
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7301541 |
Programmable processor and method with wide operations
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7290153 |
System, method, and apparatus for reducing power consumption in a microprocessor
Included in this disclosure is a circuit for reducing power consumption in a microprocessor. The circuit comprises a microprocessor, at least one full instruction decoder configured to decode a...
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7290120 |
Microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer
A microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer is disclosed. The microprocessor...
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7284115 |
Processor which overrides default operand size for implicit stack pointer references and near branches
A processor supports a mode in which the default operand size is 32 bits, but which supports operand size overrides to 64 bits. Furthermore, the default operand size may automatically be overridden...
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7263621 |
System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback
The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit...
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7254696 |
Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests
A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC...
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7246218 |
Systems for increasing register addressing space in instruction-width limited processors
A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file,...
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7228403 |
Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture
A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength...
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7216218 |
Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations
The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and...
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7216138 |
Method and apparatus for floating point operations and format conversion operations
A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of...
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7213129 |
Method and system for a two stage pipelined instruction decode and alignment using previous instruction length
A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for...
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7206921 |
Micro-operation un-lamination
A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The...
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7197625 |
Alignment and ordering of vector elements for single instruction multiple data processing
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a...
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7194602 |
Data processor
A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a...
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7149879 |
Processor and method of automatic instruction mode switching between n-bit and 2n-bit instructions by using parity check
A processor and method of automatic instruction mode switching between N-bit and 2N-bit instructions by using parity bit check. The processor and method includes an instruction input device having...
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7133040 |
System and method for performing an insert-extract instruction
An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is...
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7120779 |
Address offset generation within a data processing system
A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction...
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7103754 |
Computer instructions for having extended signed displacement fields for finding instruction operands
A computer architecture that provides the definition of a 20 bit signed displacement value used to form the operand storage address.
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7089393 |
Data processing using a coprocessor
A data processing system using a main processor 8 and a coprocessor 10 provides coprocessor load instructions (USALD) for loading a variable number of data values dependent upon alignment into...
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7080235 |
Device and method for generating and executing compressed programs of a very long instruction word processor
A method for controlling functional units in a processor, according to which in a configuration a sequence of primary instruction words which consists of several instruction word parts and...
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