Matches 251 - 300 out of 392 < 1 2 3 4 5 6 7 8 >
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5961632 Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes  
A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines...
5956494 Method, apparatus, and computer instruction for enabling gain control in a digital signal processor  
A digital signal processor (10) for implementing a gain instruction. The gain instruction, when decoded, controls a multiplexer (43) to select a gain control index signal. The value of the chosen...
5951674 Object-code compatible representation of very long instruction word programs  
Object-code compatibility is provided among VLIW processors with different organizations. The object-code can also be executed by sequential processors, thus providing compatibility with scalar and...
5948096 Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes  
A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length...
5941982 Efficient self-timed marking of lengthy variable length instructions  
A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders...
5941980 Apparatus and method for parallel decoding of variable-length instructions in a superscalar pipelined data processing system  
A process is provided for determining the beginning and ending of each instruction of a variable length instruction. Data lines are stored in a first memory area which illustratively is an...
5931941 Interface for a modularized computational unit to a CPU  
A way of designing CPU's and computational units in an integrated circuit so that the computational unit can be designed and connected to the CPU in a modular manner. The computational unit...
5931944 Branch instruction handling in a self-timed marking system  
An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling...
5930508 Method for storing and decoding instructions for a microprocessor having a plurality of function units  
A method and apparatus for compacting VLIW instructions in a processor having multiple functional units and including a buffer for storing compacted instructions, wherein NOP codes are eliminated...
5930790 String-match array for substitutional compression  
A circuit for implementing a substitutional compressor. Comparators compare a current input pixel against a large number of previous pixels, the "history", stored in a series of shift registers....
5930521 Reorder buffer architecture for accessing partial word operands  
A reorder buffer for an out-of-order issue/execute superscalar microprocessor is composed of a destination register unit, four data units, and a destination tag unit. The destination register and...
5925122 Data processing unit which pre-fetches instructions of different lengths to conduct processing  
A data processing unit including instruction queue circuits for pre-fetching instructions from a memory and an immediate generator for receiving input of immediate data of an instruction held by...
5920713 Instruction decoder including two-way emulation code branching  
An instruction decoder includes an emulation code sequencer and emulation code ROM for handling various instructions. The emulation code ROM includes a sequence of operations (Op) and an operation...
5918034 Method for decoupling pipeline stages  
The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination...
5909588 Processor architecture with divisional signal in instruction decode for parallel storing of variable bit-width results in separate memory locations  
An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division...
5907694 Data processing apparatus for performing a pipeline operation on a load and extension instruction  
The present data processing apparatus effects the pipeline operation for each of the machine cycle time with a plurality of pipeline stages processed in parallel. With respect to a load & extension...
5905893 Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set  
A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length...
5905880 Robust multiple word instruction and method therefor  
An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word...
5898851 Method and apparatus for five bit predecoding variable length instructions for scanning of a number of RISC operations  
A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode...
5890006 Apparatus for extracting instruction specific bytes from an instruction  
A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. In one embodiment, to expedite the dispatch of instructions, the...
5881259 Input operand size and hi/low word selection control in data processing systems  
A data processing system having a plurality of registers 10 and an arithmetic logic unit 20, 22, 24 includes program instruction words having a source register bit field Sn specifying one of the...
5881260 Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction  
An apparatus and method are shown for decoding variable length instructions in a processor where a line of variable length instructions from an instruction cache are loaded into an instruction...
5872985 Switching multi-context processor and method overcoming pipeline vacancies  
An instruction executing section supplies an instruction of a certain context to a pipeline and executes the context. When a vacancy of the pipeline is judged, the instruction executing section...
5870578 Workload balancing in a microprocessor for reduced instruction dispatch stalling  
A microprocessor employs a set of symmetrical functional units, each of which is coupled into an issue position. Instructions are fetched and aligned to the issue positions. During clock cycles in...
5870576 Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures  
Methods apparatus for storing and expanding wide instruction words in a computer system are provided. The computer system includes a memory and an instruction cache. Compressed instruction words of...
5867682 High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations  
A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and...
5867681 Microprocessor having register dependent immediate decompression  
A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length...
5864704 Multimedia processor using variable length instructions with opcode specification of source operand as result of prior instruction  
A media engine is disclosed herein which incorporates into a single chip structure the seven multimedia functions of video, 2D graphics, 3D graphics, audio, FAX/modem, telephony, and...
5862398 Compiler generating swizzled instructions usable in a simplified cache layout  
The software which produces a shuffled bit stream which bit stream allows for a simplified cache layout. This object is met using computer software which includes code for receiving a compiled and...
5859992 Instruction alignment using a dispatch list and a latch list  
An instruction alignment unit includes a byte queue configured to store instruction blocks. Each instruction block includes a fixed number of instruction bytes and identifies up to a maximum number...
5857088 System for configuring memory space for storing single decoder table, reconfiguring same space for storing plurality of decoder tables, and selecting one configuration based on encoding scheme  
Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data...
5854919 Processor and its operation processing method for processing operation having bit width exceeding data width of bit storage unit  
The processor comprises a storage unit for accommodating data required for operations and operation results and an arithmetic unit for processing an operation using operation data read from the...
5854913 Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set architectures  
A microprocessor which supports two distinct instruction-set architectures. The microprocessor includes a mode control unit which enables extensions and/or limitations to each of the two...
5852727 Instruction scanning unit for locating instructions via parallel scanning of start and end byte information  
An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a...
5848288 Method and apparatus for accommodating different issue width implementations of VLIW architectures  
A method and apparatus which permits a computer system to execute variable size instruction bundles. A processor fetches an instruction issue group of the size it can issue in one cycle. By...
5845099 Length detecting unit for parallel processing of variable sequential instructions  
A microprocessor with a circuit that selects at least one instruction from a stream of N successive instruction bytes. The circuit includes a first pointing unit that indicates a position of a...
5845102 Determining microcode entry points and prefix bytes using a parallel logic technique  
A superscalar microprocessor implements a microcode instruction unit with an MROM entry point generator. The MROM entry point generator generates the first address of a microcode sequence that...
5828873 Assembly queue for a floating point unit  
A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses...
5828859 Method and apparatus for setting the status mode of a central processing unit  
Data for designating a status mode is written beforehand in a data portion of a data-type microinstruction. When power is introduced, first, the data type microinstruction is read. Next, a...
5826053 Speculative instruction queue and method therefor particularly suitable for variable byte-length instructions  
A speculative instruction queue for a superscalar processor of the type having a variable byte-length instruction format, such as the X86 format, is organized as a 16-byte FIFO. The head of the...
5822552 Method and circuit for rearranging output data in variable-length decoder  
The invention relates to a method and a circuit for rearranging output data of a variable-length decoder (VLD). The circuit for rearranging output data of a VLD has an internal memory, a first data...
5822555 Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer  
A circuit and method for supplying and aligning a block of multiple variable length macro instructions to an instruction buffer. Only one cycle is required to align and rotate the block of...
5819057 Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units  
A high performance superscalar microprocessor including an instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of...
5819056 Instruction buffer organization method and system  
Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction...
5819059 Predecode unit adapted for variable byte-length instruction set processors and method of operating the same  
A superscalar microprocesor is provided that includes a predecode unit adapted for predecoding variable byte-length instructions. The predecode unit predecodes the instructions prior to their...
5819058 Instruction compression and decompression system and method for a processor  
A system and method for compressing and decompressing variable length instructions contained in variable length instruction packets in a processor having a plurality of processing units is provided...
5809272 Early instruction-length pre-decode of variable-length instructions in a superscalar processor  
A superscalar processor can dispatch two instructions per clock cycle. The first instruction is decoded from instruction bytes in a large instruction buffer. A secondary instruction buffer is...
5809273 Instruction predecode and multiple instruction decode  
Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by predecoding each byte of an instruction, assuming each byte to be an...
5809274 Purge control for ON-chip cache memory  
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the...
5799138 Apparatus for instruction-word-linK compression  
A digital data processing apparatus comprising a memory and a central processing unit. The digital data processing apparatus includes a code conversion section. The code conversion section assigns...
Matches 251 - 300 out of 392 < 1 2 3 4 5 6 7 8 >