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6195746 |
Dynamically typed register architecture
Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated...
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6195740 |
Constant reconstructing processor that execute an instruction using an operand divided between instructions
A processor for decoding and executing an instruction includes: an instruction register 10 for storing an instruction; a format decoder 21 for decoding a format code located in the P0.0 field 11 of...
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6185671 |
Checking data type of operands specified by an instruction using attributes in a tagged array architecture
The present invention discloses a method and apparatus for matching data types of operands in an instruction. A type code of an operand used by the instruction is determined. An attribute value of...
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6182202 |
Generating computer instructions having operand offset length fields for defining the length of variable length operand offsets
A method and apparatus for storing a variable length operand offset in a computer instruction is provided. An operand base is stored in a computer instruction. Also stored in the computer...
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6178496 |
System for converting instructions, and method therefore
A converter (130) comprises a multiplex-buffer (410) at a bus (120), a decoder (420), an output buffer (430) and a comparator (440). The multiplex-buffer (410) forwards V MAX bits (260) of Huffman...
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6178491 |
Method for storing data structures in memory using address pointers, and apparatus
A compiler system (190) stores a data structure (101, e.g., a program) to a memory (110) of an execution system (100). The data structure (101) comprises, for example, processor instructions coded...
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6175907 |
Apparatus and method for fast square root calculation within a microprocessor
An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a...
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6175909 |
Forwarding instruction byte blocks to parallel scanning units using instruction cache associated table storing scan block boundary information for faster alignment
A microprocessor configured to use historical scan information to speed instruction scanning is disclosed. The microprocessor may comprise an instruction cache, a scanning history table, routing...
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6170050 |
Length decoder for variable length data
A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length decoder includes a length estimator and a...
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6138202 |
Object space manager circuit for obtaining addresses of object headers
The object space manager circuit is a device used in computer memory systems for determining the address of the first word of an object, given the address of any other word in the same object. It...
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6134650 |
Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data
A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. When the cache line is scanned for dispatch, the first scanned...
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6131152 |
Planar cache layout and instruction stream therefor
Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met...
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6128614 |
Method of sorting numbers to obtain maxima/minima values with ordering
A technique for sorting packed numbers of two operands into minima or maxima operand with their indices to identify the origin of those selected values. After packing two source operands with a...
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6128726 |
Accurate high speed digital signal processor
An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions...
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6125441 |
Predicting a sequence of variable instruction lengths from previously identified length pattern indexed by an instruction fetch address
An instruction cache having a pattern detector for use in predicting the length of variable length instructions in a microprocessor. The instruction cache comprises an instruction length...
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6115808 |
Method and apparatus for performing predicate hazard detection
Performing hazard detection using status and mask vectors. Predicate status and mask vectors are generated. From the predicate status vector it is determined if a predicate is pending, and from the...
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6115806 |
Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel
In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of...
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6105126 |
Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code
A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular...
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6105125 |
High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information
A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers....
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6101598 |
Methods for debugging a multiprocessor system
A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is...
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6101596 |
Information processor for performing processing without register conflicts
An information processor is capable of eliminating register conflict in short and long latency processes and for attaining high-speed pipeline processing through efficient use of registers. The...
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6092183 |
Data processor for processing a complex instruction by dividing it into executing units
A compact and small compensating-electric-power data processor is realized by dividing a plurality of calculations to be carried out by a complex instruction into a number of executing units to be...
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6085308 |
Protocol processor for the execution of a collection of instructions in a reduced number of operations
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor...
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6085313 |
Computer processor system for executing RXE format floating point instructions
A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is...
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6085316 |
Layered counterflow pipeline processor with anticipatory control
A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the...
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6070237 |
Method for performing population counts on packed data types
A novel processor for manipulating packed data. The packed data includes a first data element D1 and a second data element D2. Each of said data elements has a predetermined number of bits. The...
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6049863 |
Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor
A predecode unit is configured to predecode variable byte-length instructions prior to their storage within an instruction cache of a superscalar microprocessor. The predecode unit generates three...
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6041176 |
Emulation devices utilizing state machines
An emulation device which enables a functional circuit to support self emulation. A serial scan testability interface has at least first, second and third scan paths, said first scan path being...
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6041405 |
Instruction length prediction using an instruction length pattern detector
A microprocessor configured to predict the length of variable length instructions for decoding purposes by detecting patterns of instruction lengths that have been previously decoded. The...
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6041403 |
Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction
A method and apparatus for decoding a macroinstruction, the macroinstruction including an operational code (opcode) and a specification of an operand, is described. The method includes two primary...
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6041404 |
Dual function system and method for shuffling packed data elements
An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data...
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6035387 |
System for packing variable length instructions into fixed length blocks with indications of instruction beginning, ending, and offset within block
A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion....
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6032250 |
Method and apparatus for identifying instruction boundaries
A method and device for identifying boundaries between variable length instructions in a packet of instruction bytes includes examining each instruction byte in a first portion of the packet,...
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6026486 |
General purpose processor having a variable bitwidth
A 32-bit processor control unit receives from a memory an instruction. The control unit then determines whether the received instruction is intended for a 32-bit processor or for a 16-bit...
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6021438 |
License management system using daemons and aliasing
A license restriction management system having wrapper programs and agents as appropriate to manage launches of application programs in distributed systems of computers having a multiplicity of...
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6021265 |
Interoperability with multiple instruction sets
Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing...
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6018799 |
Method, apparatus and computer program product for optimizing registers in a stack using a register allocator
Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by...
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6014735 |
Instruction set extension using prefixes
The present invention discloses a method and apparatus for encoding an instruction in an instruction set which uses a prefix code to qualify an existing opcode of an existing instruction. An opcode...
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6014740 |
Single instruction method of seizing control of program execution flow in a multiprocessor computer system
A single-instruction method of diverting or "hooking" the operation of software entails setting up a work area of code at an address within the range of a relative branching instruction type...
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6012134 |
High-performance processor with streaming buffer that facilitates prefetching of instructions
A computer processor with a mechanism for improved prefetching of instrucns into a local cache includes an instruction pointer multiplexer that generates one of a plurality of instruction pointers...
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6006300 |
System for isolating high-band-width signals transmitted between latency and jitter sensitive devices coupled to a secondary bus from operations on a primary bus
A multimedia terminal for processing multimedia signals having a host processor, latency, jitter insensitive and latency, jitter sensitive devices, and an isolation device between the latency and...
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6003125 |
High performance adder for multiple parallel add operations
An adder unit for a microprocessor, being capable, in response to a first control signal, of adding two full word data values, stored in a first storage location and in a second storage location,...
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5991874 |
Conditional move using a compare instruction generating a condition field
An apparatus for use in a computer system comprises a first storage area and a circuit, coupled to the first storage area, configured to perform a comparison of a data element A with a data element...
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5987235 |
Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions
A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode...
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5983340 |
Microprocessor system with flexible instruction controlled by prior instruction
A data processing apparatus having a pipeline computer architecture with an input pipeline latch is disclosed. The data processing apparatus includes an ALU that executes a plurality of processing...
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5983336 |
Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to designated execution units groups
An unpacking circuit and operating method in a very long instruction word (VLIW) processor provides for parallel handling of a packed wide instruction in which a packed wide instruction is divided...
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5978899 |
Apparatus and method for parallel processing and self-timed serial marking of variable length instructions
Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction...
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5968165 |
System and method for minimizing the size of operands
A dynamic word size processing system which determines for each instruction the number of cycles required by a data path to compute the result. Values in a register file are augmented with...
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5966544 |
Data speculatable processor having reply architecture
A microprocessor having a replay architecture with an execution core for performing data speculation in executing an instruction, a delay unit for making a copy of the instruction and holding the...
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5964861 |
Method for writing a program to control processors using any instructions selected from original instructions and defining the instructions used as a new instruction set
A method for designing a processor. The method utilises the full flexibility of an original instruction set in writing programs for operation of the processor the subset of instruction words used...
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