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6401194 Execution unit for processing a data stream independently and in parallel  
A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic...
6397319 Process for executing highly efficient VLIW  
A 32-bit instruction 50 is composed of a 4-bit format field 51 , a 4-bit operation field 52 , and two 12-bit operation fields 59 and 60 . The 4-bit operation field 52 can only include (1)...
6397323 Data processor having an instruction decoder  
In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of...
6393552 Method and system for dividing a computer processor register into sectors  
A method and implementing system are provided in which processor registers are divided into sectors and such sectors are individually renamed. In one embodiment, the register file is divided into...
6393501 Microprocessor with external memory interface optimized by an early decode system  
A microprocessor circuit having an external memory interface includes a transmission element for the transmission of binary data packets between the microprocessor and the interface. The interface...
6370636 Accessing byte lines from dual memory blocks and aligning for variable length instruction execution  
A data access circuit for a CPU that individually extracts and processes variable length data or commands from a memory in one clock period provides high speed processing. The circuit includes a...
6369723 Replacement of special characters in a data stream  
In rows ( 1 ) of data elements ( 11, 12 ), there may occur special data elements, such as control characters. By replacing each special data element ( 12 ) by a replacement data element ( 14 ),...
6367003 Digital signal processor having enhanced utilization of multiply accumulate (MAC) stage and method  
A digital signal processor (DSP) architecture which allows the DSP Multiply-Accumulator (MAC) to be used for special fixed functions during those times when the programmable portions of the DSP are...
6360317 Predecoding multiple instructions as one combined instruction and detecting branch to one of the instructions  
A microprocessor detects a floating point exchange instruction followed by a floating point instruction and dispatches the two instructions to the floating point unit as one combined instruction....
6349379 System for executing instructions having flag for indicating direct or indirect specification of a length of operand data  
The present invention discloses an image processor ( 224 ) for executing a computer instruction set ( 280, 290 ) in the form of an opcode ( 281 ), at least one operand ( 283-285 ) which is, or...
6339821 Data processor capable of handling an increased number of operation codes  
A data processor is provided to increase the number of instructions it can handle, even with a large number of operands required for the instructions. The data processor comprises a decoding...
6338136 Pairing of load-ALU-store with conditional branch  
An apparatus and method are provided for executing a compare-and-jump operation in a pipeline microprocessor. Typically, the compare-and-jump operation is specified by two micro instructions. The...
6317822 Instruction encoding techniques for microcontroller architecture  
Code and instruction encoding extensions to a microcontroller architecture provide backward compatibility with an existing microcontroller while allowing significant performance enhancements as a...
6317825 Microprocessor comprising bit concatenation means  
The invention relates to a microprocessor (MP) comprising means to decode (DEC1) a compact instruction (BMV) for the concatenation of at least one bit (b i ) of a first binary word (W1) with at...
6313766 Method and apparatus for accelerating software decode of variable length encoded information  
A method and apparatus to accelerate variable length decode is disclosed. The system includes a logic device to receive a bit stream of variable length encoded information. The logic device outputs...
6314510 Microprocessor with reduced context switching overhead and corresponding method  
A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working...
6308257 Method and apparatus for generating boundary markers for an instruction stream including variable-length instructions  
A method of generating boundary markers, for an instruction stream including variable-length instructions, includes generating a number of sets of potential boundary markers for a predetermined set...
6308258 Data processing circuit with target instruction and prefix instruction  
A certain target instruction and a prefix instruction for expanding the function of that target instruction are input to the present data processing circuit. The data processing circuit analyses...
6301654 System and method for permitting out-of-order execution of load and store instructions  
In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned...
6295599 System and method for providing a wide operand architecture  
The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either...
6292845 Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively  
An instruction fetching unit is described for loading instructions from a memory processed by a data processing device. The instruction code can be of at least two different lengths, and each...
6292881 Microprocessor, operation process execution method and recording medium  
A microprocessor capable of executing a process instruction having at least one RISC type instruction is constructed to include an instruction decoding section for decoding a microcode including...
6282634 Apparatus and method for processing data having a mixed vector/scalar register file  
A floating point unit is provided with a register bank comprising 32 registers that may be used as either vector registers of scalar registers. A data processing instruction includes at least one...
6282633 High data density RISC processor  
A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average...
6275749 Interrupt-controlled thread processing  
Rapid thread processing is performed by associating thread contexts stored in a remote memory with interrupts for controlling the operation of a hardware-accelerated processor. This both minimizes...
6275926 System and method for writing back multiple results over a single-result bus and processor employing the same  
For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a system for, and method of, writing back the results of...
6275921 Data processing device to compress and decompress VLIW instructions by selectively storing non-branch NOP instructions  
A data processing device includes an instruction storage memory which stores load instructions by eliminating NOP instructions for insertion into a load module of a VLIW computer. The data...
6266768 System and method for permitting out-of-order execution of load instructions  
In a load/store unit within a microprocessor, load instructions are executed out of order. The load instructions are assigned tags in a predetermined manner, and then assigned to a load reorder...
6263429 Dynamic microcode for embedded processors  
A method of compressing programs, especially those used in embedded systems, is provided which allows greater program compression without significantly degrading system performance. The method...
6260133 Processor having operating instruction which uses operation units in different pipelines simultaneously  
An instruction fetch unit 10 issues a normal ALU operating instruction or a wide ALU operating instruction using two operating units to a first pipeline 14. The instruction fetch unit 10 also...
6260134 Fixed shift amount variable length instruction stream pre-decoding for start byte determination based on prefix indicating length vector presuming potential start byte  
A predecode unit is configured to predecode a fixed number of instruction bytes of variable length instructions per clock cycle. The predecode unit outputs predecode bits which identify the start...
6253312 Method and apparatus for double operand load  
An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic,...
6253309 Forcing regularity into a CISC instruction set by padding instructions  
A microprocessor configured to rapidly decode variable-length instructions is disclosed. The microprocessor is configured with a predecoder and an instruction cache. The predecoder is configured to...
6253305 Microprocessor for supporting reduction of program codes in size  
A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an...
6253308 Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word  
A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the...
6253287 Using three-dimensional storage to make variable-length instructions appear uniform in two dimensions  
A microprocessor capable of predecoding variable-length instructions and storing them in a three-dimensional instruction cache is disclosed. The microprocessor may comprise a predecode unit, an...
6247112 Bit manipulation instructions  
Methods and systems for bit manipulation instructions are disclosed. The instruction srlmsk shifts a value stored in a first register based on a shift value stored in a second register and loads N...
6243803 Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry  
A method and apparatus for computing a Packed Absolute Differences. According to one such method and apparatus, a third packed data having a third plurality of elements and the plurality of sign...
6240509 Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation  
In one embodiment of the invention, a processor includes an execution pipeline to execute instructions, wherein at least some of the instructions are executed speculatively. The processor also...
6240506 Expanding instructions with variable-length operands to a fixed length  
A microprocessor configured to predecode instructions with variable address and operand lengths into a uniform format with constant address and operand lengths is disclosed. The microprocessor may...
6237074 Tagged prefetch and instruction decoder for variable length instruction set and method of operation  
A pipelined processor in which the decoder can consume a portion of an instruction and hold that portion in sub-field shadow registers while retrieving the remainder of the instruction in a...
6237080 Executable programs  
A computer having a reduced instruction computer (RISC) architecture has a RISC central processing unit (CPU)(1) coupled to a RAM memory (3) and to a flash ROM memory (4). A set of compressed...
6233671 Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions  
A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro...
6230256 Data processing system having a bus wider than processor instruction width  
A data processing system contains a processor supporting instructions and operands utilizing a Narrow word size. The processor communicates over a bus utilizing a Wide word size with the remainder...
6223254 Parcel cache  
The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a...
6219779 Constant reconstructing processor which supports reductions in code size  
A processor includes a constant register 36 for storing a constant, a format decoder 21 for decoding a format code located in the P0.0 field of an instruction stored in the instruction register 10,...
6212621 Method and system using tagged instructions to allow out-of-program-order instruction decoding  
A microprocessor configured to allow instructions to be decoded out of order is disclosed. The microprocessor is configured to assign fetch tags to groups of instruction bytes as they are fetched...
6212601 Microprocessor system with block move circuit disposed between cache circuits  
In one embodiment, there is a single integrated circuit microprocessor (10). The microprocessor has an instruction pipeline (12) which comprises an execution stage (12a) operable to process an...
6205534 Apparatus and method for processing data with a plurality of flag groups  
In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups...
6202143 System for fetching unit instructions and multi instructions from memories of different bit widths and converting unit instructions to multi instructions by adding NOP instructions  
A data processing system for processing digital data comprises a first program bus for transferring a unit instruction, a second program bus for transferring a multi instruction consisting of unit...
Matches 151 - 200 out of 392 < 1 2 3 4 5 6 7 8 >