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6684322 Method and system for instruction length decode  
A system and method for decoding the length of a macro instruction is described. In one embodiment, the system comprises an opcode-plus-immediate logic unit to generate a first length value, the...
6684320 Apparatus and method for issue grouping of instructions in a VLIW processor  
An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW...
6678818 Decoding next instruction of different length without length mode indicator change upon length change instruction detection  
A decode unit ( 20 ) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a...
6675235 Method for an execution unit interface protocol and apparatus therefor  
An execution unit ( 2 ) interface protocol allowing flow-through of data, where a function is specified once and the execution unit performs the function for multiple sets of input data. Function...
6662087 Backward compatible diagnostic tool  
A test instrument includes a cartridge adapter for receiving existing vehicle diagnostic cartridges programmed for use with an 8-bit microprocessor. The adapter is coupled to a field programmable...
6658553 Universal pointer implementation scheme for uniformly addressing distinct memory spaces in a processor's address space  
A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional...
6654874 Microcomputer systems having compressed instruction processing capability and methods of operating same  
Microcomputer systems include an instruction processor therein that can process both normal length instructions and compressed instructions. The normal length instructions and the compressed...
6654869 Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling  
A microprocessor includes a fetch unit, an instruction cracking unit, and dispatch and completion control logic. The fetch unit retrieves a set of instructions from an instruction cache. The...
6654872 Variable length instruction alignment device and method  
An instruction aligner and method evaluates a fixed length instruction cache line by breaking it into at least two components. These two components, in one embodiment, include half of the...
6651159 Floating point register stack management for CISC  
A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose...
6651160 Register set extension for compressed instruction set  
Systems and methods for extending register addresses in compressed instruction sets are capable of executing extended register instructions that supplement the bits needed to address registers. The...
6647462 Apparatus and a method for providing decoded information  
An apparatus and a method for providing decoded information, the apparatus comprising: a memory module for storing encoded information; a decoder, coupled to the memory module, for fetching and...
6643744 Method and apparatus for pre-fetching audio data  
An audio system includes a memory storing audio data and an audio signal processor for processing the audio data. Addressing circuitry addresses the memory and a pre-fetch storage area stores data...
6636959 Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition  
A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides information for the instruction beginning at the fetch address, as...
6633969 Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions  
An apparatus and method for translating variable-length instructions to fixed-length instructions. The apparatus includes instruction decompression logic and caching logic. The instruction...
6631459 Extended instruction word folding apparatus  
An apparatus includes an instruction word storage for storing a plurality of general instruction words and extended instruction words, a temporary storage unit including a plurality of buffers for...
6629230 Host interface circuit  
In a host interface circuit performing data transmission/reception between an external host controller and a device connected to the external host controller, the external host controller...
6618506 Method and apparatus for improved compression and decompression  
A method and apparatus for compression and decompression of information, such as groups of computer program instructions, encodes (compresses) information comprising a plurality of units by...
6615339 VLIW processor accepting branching to any instruction in an instruction word set to be executed consecutively  
A VLIW processor includes an instruction decode unit selecting one of parallel execution and consecutive execution and decoding a plurality of operation instructions included in an instruction...
6609168 Bus master read request adaptive prefetch prediction method and apparatus  
An apparatus and method for predicting quantities of data required by requesting devices capable of requesting unspecified quantities of data from storage device, in which prediction of quantities...
6598154 Precoding branch instructions to reduce branch-penalty in pipelined processors  
A method of reducing the branch penalty in a microprocessor includes predecoding the instruction to determine whether an instruction is a branch, the length of the instruction, and prediction...
6587939 Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions  
An information processing apparatus is provided with a executable instruction extracting unit which is reconfigured by means of a executable instruction extracting unit reconfiguration unit with...
6581152 Methods and apparatus for instruction addressing in indirect VLIW processors  
An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed...
6581154 Expanding microcode associated with full and partial width macroinstructions  
A microarchitecture for dynamically expanding and executing microcode routines is provided. According to one aspect of the present invention, a mechanism expands a generic instruction into specific...
6571330 Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor  
A processor supports a processing mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64...
6564314 Computer instruction compression  
A computer system has compact instructions avoiding the need for redundant bit locations and needing simple decoding. Logic circuitry is arranged to respond to an instruction set comprising a...
6560692 Data processing circuit, microcomputer, and electronic equipment  
The data processing circuit of this invention enables efficient description and execution of processes that act upon the stack pointer, using short instructions. It also enables efficient...
6560694 Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode  
A processor supports an operating mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64...
6557096 Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types  
A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support...
6546478 Line predictor entry with location pointers and control information for corresponding instructions in a cache line  
A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch...
6539470 Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same  
An instruction decode unit is described including circuitry coupled to receive an instruction. The instruction identifies multiple operands, one of which is a destination operand. The circuitry...
6523108 Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string  
Deposit and extract instructions include an opcode, a source address, a destination address, a shift number, and a K-bit mask string. The opcode describes the operations to be performed upon a...
6504495 Clipping data values in a data processing system  
A clipping and quantization technique is described for producing clipped numbers in a range of 0 to Nāˆ’1 (from unclipped numbers in a range of āˆ’0.5N to (1.5Nāˆ’1)), where N is 2 m and m is the...
6502181 Method and apparatus for an enhanced processor  
A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run...
6502182 Digital signal processing device  
A digital signal processing device applicable to a signal processing system using a CPU is mainly configured by an external memory and a digital signal processor (i.e., DSP), which are connected...
6499100 Enhanced instruction decoding  
When decoding instructions of a program to be executed in a central processing unit comprising pipelining facilities for fast instruction decoding, part of the decoding is executed or the decoding...
6499097 Instruction fetch unit aligner for a non-power of two size VLIW instruction  
The present invention provides an instruction fetch unit aligner. In one embodiment, an apparatus for an instruction fetch unit aligner includes selection logic for selecting a non-power of two...
6499099 Central processing unit method and apparatus for extending general instructions with extension data of an extension register  
A central processing unit having an extension instruction comprises a memory address, an offset and a fixed length instruction of varying immediate data. The central processing unit comprises a...
6496923 Length decode to detect one-byte prefixes and branch  
The invention provides a system and method which can be used for pre-decoding one-byte instruction prefixes and branch instruction indicators. A static line detect generates a number of instruction...
6496922 Method and apparatus for multiplatform stateless instruction set architecture (ISA) using ISA tags on-the-fly instruction translation  
A method and apparatus for providing a stateless multiplatform instruction set architecture (ISA) for use in a computer system having a processor and memory storing a control program for...
6493819 Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor  
A microprocessor includes general purpose registers which may be accessed or updated in portions. Dependencies may be created between an instruction which updates only a portion of a destination...
6466930 Method and apparatus for evaluating expressions including time-scoped operands  
A data processing method evaluates expressions, including temporally-scoped operands, to produce temporally-scoped results. Each of the temporally-scoped operands and results includes a sequence of...
6460116 Using separate caches for variable and generated fixed-length instructions  
A microprocessor configured to rapidly decode variable-length instructions is disclosed. The microprocessor is configured with a predecoder and an instruction cache. The predecoder is configured to...
6442676 Processor with different width functional units ignoring extra bits of bus wider than instruction width  
A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a...
6438680 Microprocessor  
When a decision circuit ( 217 ) incorporated in a control circuit ( 21 ) in an instruction decode unit ( 2 ) in a microprocessor ( 1 ) decides that an integer operation unit ( 4 ) can not execute a...
6425070 Variable length instruction decoder  
The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the...
6412063 Multiple-operand instruction in a two operand pipeline and processor employing the same  
For use in a processor having a pipeline of insufficient width to convey all operands of a given multiple-operand instruction concurrently, a system for, and method of, processing the...
6405303 Massively parallel decoding and execution of variable-length instructions  
A microprocessor configured to decode a plurality of instruction bytes in parallel is disclosed. The microprocessor may comprise a plurality of single-byte decoder/execution units that are...
6401144 Method and apparatus for managing data transfers between peripheral devices by encoding a start code in a line of data to initiate the data transfers  
A method and apparatus for ensuring that information transfers from memory to a peripheral device are complete prior to the peripheral device executing instructions responsive to the content of the...
6401130 Auto aggregation method for IP prefix/length pairs  
A method, apparatus and article of manufacture for aggregating a sorted list of IP prefix pairs. A prefix pair in the list is compared to a lowest IP length subnet boundary. The prefix pair is...
Matches 101 - 150 out of 392 < 1 2 3 4 5 6 7 8 >