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7069420 |
Decode and dispatch of multi-issue and multiple width instructions
In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single...
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7069422 |
Load-shift carry instruction
A shift left with carry instruction minimizes the number of instructions required for implementing a binary search. A multi-thread packet processor transfers a data packet from a flexible data...
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7069423 |
Microcomputer
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6 , and made accessible in parallel by third buses XAB and XDB and second buses...
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7062634 |
Processor and a method for handling and encoding no-operation instructions
A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in...
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7051189 |
Method and apparatus for processor code optimization using code compression
An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the...
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7051190 |
Intra-instruction fusion
Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without...
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7047396 |
Fixed length memory to memory arithmetic and architecture for a communications embedded processor system
A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width...
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7043627 |
SIMD operation system capable of designating plural registers via one register designating field
In view of a necessity of alleviating factors obstructing an effect of SIMD operation such as in-register data alignment in high speed formation of an SIMD processor, numerous data can be supplied...
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6996700 |
Microcomputer and dividing circuit
Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a...
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6970993 |
Architecture to relax memory performance requirements
The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be...
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6968430 |
Circuit and method for improving instruction fetch time from a cache memory device
A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In...
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6968402 |
System and method for storing chunks of first cache line and second cache line in a buffer in a first and second chunk order
Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache...
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6961844 |
System and method for extracting instruction boundaries in a fetched cacheline, given an arbitrary offset within the cacheline
A system and method are presented for pre-decoding (i.e., determining the address boundaries of) variable-length instructions within an instruction block fetched from memory. The instruction block...
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6944749 |
Method for quickly determining length of an execution package
A method for decoding instructions in an execution package with a processor includes using an assembler to assemble instructions into different execution packages. Each instruction has an...
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6901503 |
Data processing circuits and interfaces
An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit...
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6889312 |
Selective zero extension based on operand size
A processor supports multiple operand sizes (e.g. 8, 16, 32, and 64 bit operand sizes, in one embodiment). Additionally, the processor determines how to update a destination register when an...
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6889313 |
Selection of decoder output from two different length instruction decoders
A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to...
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6877084 |
Central processing unit (CPU) accessing an extended register set in an extended register mode
A central processing unit (CPU) is described including a register file and an execution core coupled to the register file. The register file includes a standard register set and an extended...
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6871274 |
Instruction code conversion apparatus creating an instruction code including a second code converted from a first code
A processor includes a conversion table storage unit storing therein a table used to convert to a non-compressed instruction code from an index included in a compressed instruction code, and a...
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6865664 |
Methods, systems, and computer program products for compressing a computer program based on a compression criterion and executing the compressed program
Embodiments of systems, methods, and computer program products are provided for compressing a computer program based on a compression criterion and executing the compressed program. For example, a...
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6865666 |
Data processing device
A data processing device having a PC controlling part for executing an operation of branch which has a first register for holding a result of decoding in an instruction decode unit, a register for...
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6850999 |
Coherency coverage of data across multiple packets varying in sizes
A coherency resolution technique enables efficient resolution of data coherency for packet data associated with a service queue of an intermediate network node. The packet data is enqueued on a...
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6832307 |
Instruction fetch buffer stack fold decoder for generating foldable instruction status information
A plurality of fold decoders are each coupled to a different set of successive entries within an instruction fetch buffer stack and check the contents of the successive entries for a variable...
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6826676 |
Extending immediate operands across plural computer instructions with indication of how many instructions are used to store the immediate operand
A programmable processing system includes a first processor for executing a first portion of an instruction, a second processor for executing a second portion of the instruction, where the second...
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6820189 |
Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
A computation core for executing programmed instructions includes an execution block for performing digital signal processor operations in response to digital signal processor instructions and for...
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6817012 |
Method of translating a source operation to a target operation, computer program, storage medium, computer and translation
A method is provided for translating a source operation to a target operation. The source operation acts on one or more source operands, each comprising a binary integer of a first bit-width. The...
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6807616 |
Memory address checking in a proccesor that support both a segmented and a unsegmented address space
A processor supports several operating modes. In at least one of the operating modes, a segmented address space is used. In at least one other operating mode, an unsegmented address space is used....
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6801995 |
Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes
A method of assigning unique instruction codes to instructions in an instruction set is disclosed. Such an encoded instruction set is also disclosed. Instructions are grouped according to the...
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6801996 |
Instruction code conversion unit and information processing system and instruction code generation method
An instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes...
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6802017 |
Partial enabling of functional unit based on data and size pair in register
An SZ (size information) section is provided for each of registers that make up a register file. Suppose an instruction decoded requests that operand data of a particular size be loaded from a RAM...
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6799265 |
Dependency checking for reconfigurable logic
A data dependency checking table is used with a reconfigurable chip. A control processing chip on the reconfigurable chip can load variable size blocks of data to and from reconfigurable slices on...
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6789184 |
Instruction address generation and tracking in a pipelined processor
In an embodiment, an address pipeline corresponding to an instruction pipeline in a processor, for example, a digital signal processor (DSP), may generate and track the instruction address of each...
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6772320 |
Method and computer program for data conversion in a heterogeneous communications network
A method and computer program for data conversion in a heterogeneous communications network. This method and computer program converts data for computer systems having different data storage...
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6763449 |
Operation-processing apparatus
An operation-processing apparatus is equipped with an instruction decoder for decoding an existing instruction and an extension instruction into the same operation code including at least...
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6751724 |
Method and apparatus for instruction fetching
Embodiments of the present invention relate to instruction fetching in data processing systems. One aspect involves a data processor ( 202 ) to execute instructions and to fetch instructions from a...
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6745319 |
Microprocessor with instructions for shuffling and dealing data
A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand ( 600 ) and storing the shuffled result in a selected...
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6742109 |
Method and apparatus for representing variable-size computer instructions
One embodiment of the present invention provides a system for executing variable-size computer instructions, wherein a variable-size computer instruction includes an action component that specifies...
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6742131 |
Instruction supply mechanism
An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit...
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6732258 |
IP relative addressing
A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an...
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6732257 |
Reducing the length of lower level instructions by splitting and recombining an immediate
A method is disclosed in which a higher level instruction having an immediate is read from memory and translated into two lower level instructions. The first is to move a first portion of the...
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6725356 |
System with wide operand architecture, and method
The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either...
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6721875 |
Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form
Disclosed is a computer architecture with single-syllable IP-relative branch instructions and long IP-relative branch instructions (IP=instruction pointer). The architecture fetches instructions in...
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6718456 |
Parallel pack instruction method and apparatus
Disclosed herein is a apparatus and method for packing a 16-bit number into an 8-bit result byte. The method and apparatus utilize a parallel processing right shift circuit and a filter to obtain...
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6718452 |
Storage array supporting a plurality of instruction modes
A storage array is described which is specifically adapted to support a specific set of instruction modes of a processor. A first set of storage cells have a write input and a single read output....
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6715061 |
Multimedia-instruction acceleration device for increasing efficiency and method for the same
The present invention proposes a multimedia-instruction acceleration device for increasing efficiency and a method for the same, which uses instruction strings having a floating-point value check...
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6704833 |
Atomic transfer of a block of data
A method for transferring data between a processor and a memory includes (A) executing, at the processor, an instruction that includes (i) a specifier of a location in a storage resource local to...
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6704855 |
Method and apparatus for reducing encoding needs and ports to shared resources in a processor
The present invention relates to a method for accessing elements from a shared resource to be used by consumers that perform actions according to corresponding operations. The method creates a...
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6704854 |
Determination of execution resource allocation based on concurrently executable misaligned memory operations
A processor includes execution resources for handling a first memory operation and a concurrent second memory operation. If one of the memory operations is misaligned, the processor may allocate...
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6704859 |
Compressed instruction format for use in a VLIW processor
A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format...
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6694423 |
Prefetch streaming buffer
A data processing unit having superscalar structure able to execute a plurality of instructions in parallel includes a memory for storing the instructions having a plurality of n-bit input/output...
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