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7624382 |
Method and system of control flow graph construction
A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction...
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7617088 |
Interpage prologue to protect virtual address mappings
In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier...
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7613903 |
Data processing device with instruction translator and memory interface device to translate non-native instructions into native instructions for processor
A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The...
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7606997 |
Method and system for using one or more address bits and an instruction to increase an instruction set
A method and system for expanding an instruction set by decoding an instruction located at a particular address using one or more of those address bits in conjunction with the instruction word.
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7594098 |
Processes and devices for compression and decompression of executable code by a microprocessor with RISC architecture and related system
An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into...
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7590832 |
Information processing device, compressed program producing method, and information processing system
An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the...
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7590829 |
Extension adapter
A processor system. The processor system comprises a processor having a first set of instructions associated therewith. The processor system also comprises a programmable logic device and an...
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7565513 |
Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations
A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and...
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7552426 |
Systems and methods for using synthetic instructions in a virtual machine
The present invention compensates for the shortcomings in x86 processor architectures by providing a set of “synthetic instructions” that cause a trap and thereby provide an opportunity for the...
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7543287 |
Using a block device interface to invoke device controller functionality
In one embodiment, a standard block device command is received at a device controller. The standard block device command is addressed to a virtual block device associated with the device...
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7539844 |
Prefetching indirect array accesses
A method for prefetching data from an array, A, the method including: detecting a stride, dB, of a stream of index addresses of an indirect array, B, contents of each index address having...
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7536682 |
Method and apparatus for performing interpreter optimizations during program code conversion
A translator apparatus is provided with both program code interpreting and translating functionality, where subject program code is interpreted rather than being translated in those situations...
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7536534 |
Processor capable of being switched among a plurality of operating modes, and method of designing said processor
A processor has an instruction set A and an instruction set B. A system instruction decoder decodes a system instruction that specifies the operating mode of the processor, the system instruction...
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7533250 |
Automatic operand load, modify and store
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode...
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7529912 |
Apparatus and method for instruction-level specification of floating point format
Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an...
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7526633 |
Method and system for encoding variable length packets with variable instruction sizes
Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction...
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7509480 |
Selection of ISA decoding mode for plural instruction sets based upon instruction address
An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to...
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7502918 |
Method and system for data dependent performance increment and power reduction
A method of dispatching instructions includes dispatching original instructions into an instruction buffer, including at least one operand, renaming the operand, selecting the original instructions...
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7500085 |
Identifying code for compilation
A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch...
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7493479 |
Method and apparatus for event detection for multiple instruction-set processor
A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device...
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7493474 |
Methods and apparatus for transforming, loading, and executing super-set instructions
Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form...
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7478224 |
Microprocessor access of operand stack as a register file using native instructions
A combined native (RISC or CISC) microprocessor and stack (Java™) machine are constructed so that Java™ VM instructions can be executed in hardware. Most Java™ instructions are executed...
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7473293 |
Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator
A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes)....
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7467327 |
Method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed
A method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a...
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7447877 |
Method and apparatus for converting memory instructions to prefetch operations during a thread switch window
A method and apparatus for converting memory instructions to prefetch operations during a thread switch window is disclosed. In one embodiment, memory access instructions that are already inside an...
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7447871 |
Data access program instruction encoding
A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit...
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7434030 |
Processor system having accelerator of Java-type of programming language
In a processor system comprising of a processor having an instruction decoder 22 , a general register 61 composed of a plurality of register areas and at least one ALU 60 , and a Java...
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7428630 |
Processor adapted to receive different instruction sets
A processor has respective first and second external instruction formats (F 1 , F 2 ) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011)...
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7418580 |
Dynamic object-level code transaction for improved performance of a computer
A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level...
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7415599 |
Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location
A repeat instruction (RPT) operates on one or more operands, but the RPT instruction includes only an opcode and does not specify locations of the operand or operands. The type of operation to be...
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7398373 |
System and method for processing complex computer instructions
A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting...
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7398372 |
Fusing load and alu operations
Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a...
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7363476 |
Method and apparatus to support an expanded register set
According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing...
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7363475 |
Managing registers in a processor to emulate a portion of a stack
The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the...
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7360060 |
Using IMPDEP2 for system commands related to Java accelerator hardware
A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder...
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7353368 |
Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support
A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking...
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7353363 |
Patchable and/or programmable decode using predecode selection
Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode...
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7340588 |
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code...
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7302552 |
System for processing VLIW words containing variable length instructions having embedded instruction length identifiers
A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are...
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7301541 |
Programmable processor and method with wide operations
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7290153 |
System, method, and apparatus for reducing power consumption in a microprocessor
Included in this disclosure is a circuit for reducing power consumption in a microprocessor. The circuit comprises a microprocessor, at least one full instruction decoder configured to decode a...
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7290081 |
Apparatus and method for implementing a ROM patch using a lockable cache
A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first...
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7275028 |
System and method for the logical substitution of processor control in an emulated computing environment
In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of...
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7272700 |
Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques
An VLIW instruction mechanism is described which accesses multiple slot instructions for execution to achieve high levels of selectable parallelism and to make improvements to code density. To this...
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7263621 |
System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback
The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit...
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7260705 |
Apparatus to implement mesocode
In one embodiment, the invention provides a method for examining information about branch instructions. A method, comprising: examining information about branch instructions that reach a write-back...
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7243350 |
Speculative execution for java hardware accelerator
Conditional branch bytecodes are processed by a Virtual Machine Interpreter (VMI) hardware accelerator that utilizes a branch prediction scheme to determine whether to speculatively process...
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7243213 |
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product
A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to...
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7225322 |
Methods of microprocessor instruction result obfuscation
A CPU executes program instructions which result in valid and invalid intermediate results. By selecting the desired intermediate results, a program is able to be successfully executed. Analysis of...
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7197628 |
Method and apparatus for execution flow synonyms
A method and apparatus for utilizing multiple microcode flow synonyms or hardware flow synonyms for an instruction is disclosed. In one embodiment, a microcode synonym is created for execution on...
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