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7590832 |
Information processing device, compressed program producing method, and information processing system
An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the...
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7571300 |
Modular distributive arithmetic logic unit
A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is...
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7568083 |
Memory mapped register file and method for accessing the same
A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by...
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7555421 |
Device emulation for testing data network configurations
A system and method for providing a virtual implementation of a large scale network of devices. The invention emulates an entire network of network devices using the configuration information...
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7552316 |
Method and apparatus for compressing instructions to have consecutively addressed operands and for corresponding decompression in a computer system
The apparatus and methods improve performance in a computer system by compressing a plurality of instructions having the same function with consecutively addressed operands and decompressing the...
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7533250 |
Automatic operand load, modify and store
A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode...
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7529914 |
Method and apparatus for speculative execution of uncontended lock instructions
A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will...
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7529912 |
Apparatus and method for instruction-level specification of floating point format
Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an...
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7516304 |
Parsing-enhancement facility
An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the...
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7506322 |
System and method of utilizing a hardware component to execute an interpretive language
A system and method of executing an interpretive language in a system having a processing component with native software processes and a memory component. A hardware component is coupled with the...
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7493473 |
Method of executing instructions using first and second control units that share a state register
A method is provided for using a reconfigurable control structure that includes a hard-wired control unit configured to execute a pre-defined instruction set and a programmable control unit...
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7441099 |
Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit
Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to...
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7441098 |
Conditional execution of instructions in a computer
A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation...
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7437532 |
Memory mapped register file
A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by...
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7434035 |
Method and system for processing instructions in grouped and non-grouped modes
An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor...
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7430678 |
Low power operation control unit and program optimizing method
An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit...
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7401204 |
Parallel Processor efficiently executing variable instruction word
A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information....
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7401176 |
Method and system for fast access to stack memory
Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit...
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7398355 |
Avoiding locks by transactionally executing critical sections
One embodiment of the present invention provides a system that avoids locks by transactionally executing critical sections. During operation, the system receives a program which includes one or...
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7395082 |
Method and system for handling events in an application framework for a wireless device
Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI...
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7389405 |
Digital signal processor architecture with optimized memory access for code discontinuity
A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code...
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7383425 |
Massively reduced instruction set processor
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to...
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7376818 |
Program translator and processor
Multiple instructions, specifying equivalent operations but designating different execution units, are stored beforehand on an instruction exchange table. First, a primary compiler compiles a...
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7376813 |
Register move instruction for section select of source operand
A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The multiplexer selects data from one section to...
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7373536 |
Fine granularity halt instruction
Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a programmer to specify which clock of a...
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7367057 |
Processor based system and method for virus detection
A processor based system and method for virus detection is described. In one embodiment, a processor comprises a plurality of functional units. The plurality of functional units includes a first...
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7363476 |
Method and apparatus to support an expanded register set
According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing...
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7350058 |
Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register
A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that...
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7346763 |
Processor instruction with repeated execution code
The present invention relates to a design of a computer system that processes instructions with a specific operation code causing the processor to execute a certain operation twice and a method for...
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7343472 |
Processor having a finite field arithmetic unit utilizing an array of multipliers and adders
A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder. The instruction memory temporarily...
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7334111 |
Method and related device for use in decoding executable code
The invention provides for a method and related device and control program for use in decoding executable code in a processing system, for example run-time operating system, including bit-shuffling...
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7308320 |
Processor core for using external extended arithmetic unit efficiently and processor incorporating the same
A processor core for realizing efficient operation processing by connecting an extended arithmetic unit to its exterior and a processor incorporating such a processing core are provided. The...
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7302597 |
Microprocessors with improved efficiency processing a variant signed magnitude format
A microprocessor is arranged to process instructions at least some of which contain at least one immediate value which forms an operand of the function, wherein said immediate value is represented...
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7301541 |
Programmable processor and method with wide operations
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7293177 |
Preventing virus infection in a computer system
A method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian™ operating system, the method comprising the steps of scanning files using...
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7290081 |
Apparatus and method for implementing a ROM patch using a lockable cache
A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first...
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7287149 |
Inserting decoder reconfiguration instruction for routine with limited number of instruction types recoded for reduced bit changes
An information processing method for coding a program to enable an information processing device having an instruction decoder having a reconfigurable circuit, comprises the steps of: simulating...
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7275147 |
Method and apparatus for data alignment and parsing in SIMD computer architecture
Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a...
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7254689 |
Decompression of block-sorted data
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
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7251722 |
Semantic processor storage server architecture
A storage server uses a semantic processor to parse and respond to client requests. A direct execution parser in the semantic processor parses an input stream, comprising client storage server...
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7246218 |
Systems for increasing register addressing space in instruction-width limited processors
A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file,...
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7231509 |
Extended register bank allocation based on status mask bits set by allocation instruction for respective code block
An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible...
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7231508 |
Configurable finite state machine for operation of microinstruction providing execution enable control value
A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in...
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7225322 |
Methods of microprocessor instruction result obfuscation
A CPU executes program instructions which result in valid and invalid intermediate results. By selecting the desired intermediate results, a program is able to be successfully executed. Analysis of...
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7213129 |
Method and system for a two stage pipelined instruction decode and alignment using previous instruction length
A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for...
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7213126 |
Method and processor including logic for storing traces within a trace cache
A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be...
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7210024 |
Conditional instruction execution via emissary instruction for condition evaluation
Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the...
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7203935 |
Hardware/software platform for rapid prototyping of code compression technologies
A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space...
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7200739 |
Generation of modified command sequence from original command by feeding back for subsequent modification based on decode control signal
A command processing device has a decoding unit, an executing unit and a providing unit. The decoding unit decodes a system command. The executing unit executes the system command and generates an...
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7191314 |
Reconfigurable CPU with second FSM control unit executing modifiable instructions
A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set...
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