|
Match
|
Document |
Document Title |
|
|
RE41012 |
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the...
|
|
|
7620749 |
Descriptor prefetch mechanism for high latency and out of order DMA device
A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support...
|
|
|
7594096 |
Load lookahead prefetch for microprocessors
The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the...
|
|
|
7587580 |
Power efficient instruction prefetch mechanism
A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than...
|
|
|
7577947 |
Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects
Methods and apparatus to dynamically insert prefetch instructions are disclosed. In an example method, one or more samples associated with cache misses are identified from a performance monitoring...
|
|
|
7562192 |
Microprocessor, apparatus and method for selective prefetch retire
An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. The microprocessor includes a prefetch buffer that stores a cache line prefetched from a system...
|
|
|
7555633 |
Instruction cache prefetch based on trace cache eviction
Various embodiments of methods and systems for implementing a microprocessor that fetches a group of instructions into instruction cache in response to a corresponding trace being evicted from the...
|
|
|
7533247 |
Operation frame filtering, building, and execution
The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the...
|
|
|
7533220 |
Microprocessor with improved data stream prefetching
A microprocessor coupled to a system memory has a memory subsystem with a translation look-aside buffer (TLB) for storing TLB information. The microprocessor also includes an instruction decode...
|
|
|
7530063 |
Method and system for code modification based on cache structure
A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining...
|
|
|
7529911 |
Hardware-based technique for improving the effectiveness of prefetching during scout mode
One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. Upon encountering a non-data dependent stall...
|
|
|
7519777 |
Methods, systems and computer program products for concomitant pair prefetching
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
|
|
|
7516312 |
Presbyopic branch target prefetch method and apparatus
An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to...
|
|
|
7516279 |
Method using stream prefetching history to improve data prefetching performance.
Computer implemented method, system and computer program product for prefetching data in a data processing system. A computer implemented method for prefetching data in a data processing system...
|
|
|
7516278 |
System controller, speculative fetching method, and information processing apparatus
A system controller, which executes a speculative fetch from a memory before determining whether data requested for a memory fetch request is in a cache by searching tag information of the cache,...
|
|
|
7511851 |
Method of and apparatus for forming an image, and computer program
The network printer obtains information from a Web page over the network, and stores this obtained information together with a URL thereof and the time when this information was received into the...
|
|
|
7509472 |
Collapsible front-end translation for instruction fetch
Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases...
|
|
|
7506105 |
Prefetching using hashed program counter
Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used...
|
|
|
7502910 |
Sideband scout thread processor for reducing latency associated with a main processor
A sideband scout thread processing technique is provided. The sideband scout thread processing technique utilizes sideband information to identify a subset of processor instructions for execution...
|
|
|
7500062 |
Fast path memory read request processing in a multi-level memory architecture
A circuit arrangement and method selectively reorder speculatively issued memory read requests being communicated to a lower memory level in a multi-level memory architecture. In particular, a...
|
|
|
7500061 |
Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program
A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to...
|
|
|
7496732 |
Method and apparatus for results speculation under run-ahead execution
A method and apparatus for using result-speculative data under run-ahead speculative execution is disclosed. In one embodiment, the uncommitted target data from instructions being run-ahead...
|
|
|
7493621 |
Context switch data prefetching in multithreaded computer
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
|
|
|
7493447 |
System and method for caching sequential programs
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
|
|
|
7490210 |
System and method for processor with predictive memory retrieval assist
A system and method for memory control. The system includes a hard-IP memory controller, a soft-IP frequency conversion system, and an interface system. The soft-IP frequency conversion system is...
|
|
|
7487296 |
Multi-stride prefetcher with a recurring prefetch table
A multi-stride prefetcher includes a recurring prefetch table that in turn includes a stream table and an index table. The stream table includes a valid field and a tag field. The stream table also...
|
|
|
7484041 |
Systems and methods for loading data into the cache of one processor to improve performance of another processor in a multiprocessor system
Systems and methods for improving the performance of a multiprocessor system by enabling a first processor to initiate the retrieval of data and the storage of the data in the cache memory of a...
|
|
|
7480783 |
Systems for loading unaligned words and methods of operating the same
Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a...
|
|
|
7472256 |
Software value prediction using pendency records of predicted prefetch values
Profile information can be used to target read operations that cause a substantial portion of misses in a program. A software value prediction technique that utilizes latency and is applied to the...
|
|
|
7461237 |
Method and apparatus for suppressing duplicative prefetches for branch target cache lines
A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second...
|
|
|
7447877 |
Method and apparatus for converting memory instructions to prefetch operations during a thread switch window
A method and apparatus for converting memory instructions to prefetch operations during a thread switch window is disclosed. In one embodiment, memory access instructions that are already inside an...
|
|
|
7441110 |
Prefetching using future branch path information derived from branch prediction
A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful...
|
|
|
7437542 |
Identifying and processing essential and non-essential code separately
A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate...
|
|
|
7430650 |
Generating a set of pre-fetch address candidates based on popular sets of address and data offset counters
Cache prefetching algorithm uses previously requested address and data patterns to predict future data needs and prefetch such data from memory into cache. A requested address is compared to...
|
|
|
7430640 |
Detecting when to prefetch inodes and then prefetching inodes in parallel
The decision to prefetch inodes is based upon the detecting of access patterns that would benefit from such a prefetch. Once the decision to prefetch is made, a plurality of inodes are prefetched...
|
|
|
7421540 |
Method, apparatus, and program to efficiently calculate cache prefetching patterns for loops
A mechanism is provided that identifies instructions that access storage and may be candidates for cache prefetching. The mechanism augments these instructions so that any given instance of the...
|
|
|
7409486 |
Storage system, and storage control method
A protocol chip and a bridge are connected to a first bus, while the bridge and a micro processor (MP) are connected to a second bus. The MP generates parameter information and writes it into a...
|
|
|
7404042 |
Handling cache miss in an instruction crossing a cache line boundary
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process...
|
|
|
7389405 |
Digital signal processor architecture with optimized memory access for code discontinuity
A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code...
|
|
|
7383417 |
Prefetching apparatus, prefetching method and prefetching program product
The efficient performance of prefetching of data prior to the reading of the data by a program. A prefetching apparatus, for prefetching data from a file to a buffer before the data is read by a...
|
|
|
7373482 |
Software-based technique for improving the effectiveness of prefetching during scout mode
One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. During operation, the system executes...
|
|
|
7370153 |
System and method of pre-fetching using an extended data structure including required data and a pre-fetch flag
Method and apparatus for implementing controlled pre-fetching of data. An extended data structure can be used to specifying where and when data is to be pre-fetched, and how much pre-fetching is to...
|
|
|
7363625 |
Method for changing a thread priority in a simultaneous multithread processor
An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in...
|
|
|
7360059 |
Variable width alignment engine for aligning instructions based on transition between buffers
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in...
|
|
|
7346762 |
Replacing instruction and corresponding instructions in a queue according to rules when shared data buffer is accessed
A method of executing program instructions may include receiving, in a processor, an instruction that causes the processor to read data from or write data to a portion of memory that is shared by...
|
|
|
7346741 |
Memory latency of processors with configurable stride based pre-fetching technique
A method and apparatus for retrieving instructions to be processed by a microprocessor is provided. By pre-fetching instructions in anticipation of being requested, instead of waiting for the...
|
|
|
7343481 |
Branch prediction in a data processing system utilizing a cache of previous static predictions
A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12 . A static branch prediction cache 30, 32, 34 is provided for storing a most...
|
|
|
7334088 |
Page descriptors for prefetching and memory management
A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a...
|
|
|
7328433 |
Methods and apparatus for reducing memory latency in a software application
Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce...
|
|
|
7328327 |
Technique for reducing traffic in an instruction fetch unit of a chip multiprocessor
A processor includes a fetch pipeline, out-of-order (OOO) logic and a strand selector. The fetch pipeline is configured to provide instructions from an instruction store to a fetch buffer...
|