Matches 1 - 50 out of 200 1 2 3 4 >
Match Document Document Title
RE41012 Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor  
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the...
7581082 Software source transfer selects instruction word sizes  
This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and 32-bit instructions can coexist in...
7552314 Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address  
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is...
7546451 Continuously providing instructions to a programmable device  
A system and method for enabling a programmable device to execute instructions without interruption. An instruction space for storing instructions from a host application is bifurcated to define a...
7509483 Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors  
A computing architecture and software techniques are described which modifies the basic sequential instruction fetching mechanism of a processor by separating a program's control flow from its...
7500088 Methods and apparatus for updating of a branch history table  
Methods and apparatus are provided for enhanced instruction handling in processing environments. If branch misprediction occurs during instruction processing, a branch history table may be updated...
7500066 Method and apparatus for sharing instruction memory among a plurality of processors  
A multiprocessing apparatus includes a memory and a plurality (M) of processors coupled to share the memory. Access to the memory is time-division multiplexed among the plurality of processors. In...
7480783 Systems for loading unaligned words and methods of operating the same  
Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a...
7454654 Multiple parallel pipeline processor having self-repairing capability  
A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a...
7454597 Computer processing system employing an instruction schedule cache  
A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the...
7424598 Data processor  
The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A...
7404048 Inter-cluster communication module using the memory access network  
An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue...
7404042 Handling cache miss in an instruction crossing a cache line boundary  
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process...
7401208 Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor  
A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream...
7401207 Apparatus and method for adjusting instruction thread priority in a multi-thread processor  
Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being...
7398374 Multi-cluster processor for processing instructions of one or more instruction threads  
The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the...
7383403 Concurrent bypass to instruction buffers in a fine grain multithreaded processor  
In one embodiment, a processor comprises a plurality of instruction buffers, an instruction cache coupled to supply instructions to the plurality of instruction buffers, and a cache miss unit...
7373536 Fine granularity halt instruction  
Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a programmer to specify which clock of a...
7366884 Context switching system for a multi-thread execution pipeline loop and method of operation thereof  
A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context...
7366874 Apparatus and method for dispatching very long instruction word having variable length  
Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer...
7363625 Method for changing a thread priority in a simultaneous multithread processor  
An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in...
7363481 Information processing method for controlling the function of a plurality of processors, program for realizing the method, and recording medium  
There is provided an information processing method characterized in that, in accordance with an instruction from a host CPU 411 , either a CPU 103 or 104 loads a common code and an instruction...
7360218 System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval  
A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction...
7360062 Method and apparatus for selecting an instruction thread for processing in a multi-thread processor  
The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor...
7350030 High performance chipset prefetcher for interleaved channels  
The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a...
7268787 Dynamic allocation of texture cache memory  
A graphics processing system has a cache which is partitionable into two or more slots. Once partitioned, the slots are dynamically allocatable to one or more texture maps. First, number of texture...
7257807 Method for optimizing execution time of parallel processor programs  
The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a...
7254689 Decompression of block-sorted data  
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
7237095 Optimum power efficient shifting algorithm for schedulers  
A method and mechanism for managing shifts in a shifting queue. A reservation station in a processing device includes a queue of shifting entries. On a given cycle, zero, one, or two instructions...
7234025 Microprocessor with repeat prefetch instruction  
A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction....
7219185 Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache  
A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of...
7194734 Method of executing an interpreter program  
A threaded interpreter executes a program having a series of program instructions stored in a memory. For the execution of a program instruction the threaded interpreter includes a preparatory unit...
7185178 Fetch speculation in a multithreaded processor  
In one embodiment, a processor comprises an instruction cache and a fetch generator circuit coupled thereto. The fetch generator circuit is configured to generate at least one fetch request to the...
7143268 Circuit and method for instruction compression and dispersal in wide-issue processors  
A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution...
7139898 Fetch and dispatch disassociation apparatus for multistreaming processors  
A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions...
7137109 System and method for managing access to a controlled space in a simulator environment  
In one embodiment, the invention may comprise a computer-implemented system for managing access to a controlled space in a simulator environment, comprising: means for requiring initialization of a...
7124318 Multiple parallel pipeline processor having self-repairing capability  
A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a...
7124282 Processor architecture with independently addressable memory banks for storing instructions to be executed  
Instructions for a processing unit are stored in a number of memory banks, successive instructions being stored in successive, different memory banks. Whenever execution of an instruction is...
7124207 I2O command and status batching  
A method and system for batching commands and status information between a host computer and an adapter installed on the host computer. The method for command batching includes the host storing...
7117343 Fetching instructions to instruction buffer for simultaneous execution with long instruction sensing or buffer overwrite control  
A program-controlled unit has a plurality of instruction-execution units for simultaneously executing successive instructions of a program that is to be executed. The program-controlled unit allows...
7107433 Mechanism for resource allocation in a digital signal processor based on instruction type information and functional priority and method of operation thereof  
A mechanism for resource allocation in a processor, a method of allocating resources in a processor and a digital signal processor incorporating the mechanism or the method. In one embodiment, the...
7096466 Loading attribute for partial loading of class files into virtual machines  
Improved techniques for loading class files into virtual computing machines are disclosed. The techniques seek to provide a mechanism that will generally improve the efficiency of virtual machines...
7062640 Instruction segment filtering scheme  
A filtering system for instruction segments determines whether a new instruction segment satisfies a predetermined filtering condition prior to storage. If the instruction segment fails the...
7039791 Instruction cache association crossbar switch  
A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied...
7039790 Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit  
A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional execution units. Fetch packets...
7028164 Instruction fetch apparatus for wide issue processors and method of operation  
There is disclosed a data processor containing an instruction issue unit that efficiently transfers instruction bundles from a cache to an instruction pipeline. The data processor comprises 1) an...
6981127 Apparatus and method for aligning variable-width instructions with a prefetch buffer  
A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined microprocessor is described. The...
6976154 Pipelined processor for examining packet header information  
A packet processing engine includes multiple microcode instruction memories implemented in parallel. For each cycle of the pipeline, an instruction from each of the memories is retrieved based on a...
6965987 System and method for handling load and/or store operations in a superscalar microprocessor  
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
6957305 Data streaming mechanism in a microprocessor  
This invention provides a dual usage cache reload buffer (CRB) to hold both demand loads as well as prefetch loads. A new form of a data cache block touch (DCBT) instruction specifies which level...
Matches 1 - 50 out of 200 1 2 3 4 >