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7620803 Data processing device and electronic equipment using pipeline control  
A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline...
7587532 Full/selector output from one of plural flag generation count outputs  
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high...
7577824 Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution  
Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions...
7555605 Data processing system having cache memory debugging support and method therefor  
A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus....
7552313 VLIW digital signal processor for achieving improved binary translation  
A VLIW digital signal processor is composed of a program memory including first to n-th banks, first to n-th address counters, a fetch block, and an instruction executing section. The first to n-th...
7518993 Prioritizing resource utilization in multi-thread computing system  
One embodiment of the present invention prioritizes resource utilization in a multi-thread processor. A priority register stores thread information for P threads. The thread information includes P...
7511712 Facilitating performance analysis for processing  
Facilitating performance analysis for processing includes capturing a state of a processing unit and capturing a plurality of commands submitted to the processing unit for processing. Both the...
7503049 Information processing apparatus operable to switch operating systems  
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed...
7502911 Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length  
A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions...
7500088 Methods and apparatus for updating of a branch history table  
Methods and apparatus are provided for enhanced instruction handling in processing environments. If branch misprediction occurs during instruction processing, a branch history table may be updated...
7500066 Method and apparatus for sharing instruction memory among a plurality of processors  
A multiprocessing apparatus includes a memory and a plurality (M) of processors coupled to share the memory. Access to the memory is time-division multiplexed among the plurality of processors. In...
7500062 Fast path memory read request processing in a multi-level memory architecture  
A circuit arrangement and method selectively reorder speculatively issued memory read requests being communicated to a lower memory level in a multi-level memory architecture. In particular, a...
7496771 Processor accessing a scratch pad on-demand to reduce power consumption  
The present invention provides processing systems, apparatuses, and methods that access a scratch pad on-demand to reduce power consumption. In an embodiment, an instruction fetch unit initiates an...
7493621 Context switch data prefetching in multithreaded computer  
An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a...
7484077 Skipping unnecessary instruction by multiplex selector using next instruction offset stride signal generated from instructions comparison results  
The present invention discloses an apparatus for removing unnecessary instruction and method thereof. The apparatus and operating method thereof include: a comparing circuit for comparing a...
7480810 Voltage droop dynamic recovery  
Method and systems for dynamically recovering from voltage droops are disclosed. In one embodiment, a microprocessor coupled to a plurality of voltage sensing circuits is provided. The...
7480783 Systems for loading unaligned words and methods of operating the same  
Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a...
7461212 Non-inclusive cache system with simple control operation  
A cache system includes a processing device operative to access a main memory device, a primary cache coupled to the processing device and accessible from the processing device at faster speed than...
7454596 Method and apparatus for partitioned pipelined fetching of multiple execution threads  
Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a...
7447876 System and method for handling load and/or store operations in a superscalar microprocessor  
The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To...
7441102 Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory  
An integrated circuit comprises a processor configured for fetching and executing opcodes, a system bus, and a memory coupled to the processor via the system bus. The memory includes logic...
7441101 Thread-aware instruction fetching in a multithreaded embedded processor  
The present invention provides a multithreaded processor, such as a network processor, that fetches instructions in a pipeline stage based on feedback signals from later stages. The multithreaded...
7434035 Method and system for processing instructions in grouped and non-grouped modes  
An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor...
7434029 Inter-processor control  
A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an...
7406585 Data processing system having an external instruction set and an internal instruction set  
There is provided a system having an execution core operable to execute internal instructions. A translation buffer is operable to store a plurality of internal instruction blocks of one or more...
7404042 Handling cache miss in an instruction crossing a cache line boundary  
A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process...
7376819 Data processor with selectable word length  
An apparatus and method for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length)....
7366875 Method and apparatus for an efficient multi-path trace cache design  
A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant...
7363625 Method for changing a thread priority in a simultaneous multithread processor  
An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in...
7356674 Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine  
A method of, and apparatus for, interfacing the hardware of a processor capable of processing instructions from more than one type of instruction set. More particularly, an engine responsible for...
7350030 High performance chipset prefetcher for interleaved channels  
The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a...
7340587 Information processing apparatus, microcomputer, and electronic computer  
An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a...
7340566 System and method for initializing a memory device from block oriented NAND flash  
Described is a system and method for initializing other memory from block oriented NAND flash by central processing units (CPUs) designed for non-NAND flash. The system employs a sequential loader...
7328329 Controlling processing of data stream elements using a set of specific function units  
A device ( 1 ) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which, during a first cycle, fetches an...
7328327 Technique for reducing traffic in an instruction fetch unit of a chip multiprocessor  
A processor includes a fetch pipeline, out-of-order (OOO) logic and a strand selector. The fetch pipeline is configured to provide instructions from an instruction store to a fetch buffer...
7293177 Preventing virus infection in a computer system  
A method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian™ operating system, the method comprising the steps of scanning files using...
7290119 Memory accelerator with two instruction set fetch path to prefetch second set while executing first set of number of instructions in access delay to instruction cycle ratio  
A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or...
7269712 Thread selection for fetching instructions for pipeline multi-threaded processor  
A simultaneous multithreading processor determines, for each thread, the processing time occupied by each thread in the processing pipeline of the processor. Based on the determined processing...
7263599 Thread ID in a multithreaded processor  
A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched...
7260704 Method and apparatus for reinforcing a prefetch chain  
A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and...
7254700 Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush  
Systems and methods for handling the event of a wrong branch prediction and an instruction rejection in a digital processor are disclosed. More particularly, hardware and software are disclosed for...
7254689 Decompression of block-sorted data  
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
7249352 Apparatus and method for removing elements from a linked list  
Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one...
7237095 Optimum power efficient shifting algorithm for schedulers  
A method and mechanism for managing shifts in a shifting queue. A reservation station in a processing device includes a queue of shifting entries. On a given cycle, zero, one, or two instructions...
7237093 Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams  
In a multi-streaming processor having a memory cache, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch...
7234025 Microprocessor with repeat prefetch instruction  
A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction....
7219185 Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache  
A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of...
7200736 Method and system for substantially registerless processing  
A simple instruction set processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller/decoder, an arithmetic logic unit, an address...
7181597 Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module  
A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A...
7178013 Repeat function for processing of repetitive instruction streams  
A REPEAT instruction for repeated execution of an associated instruction (INST R ). Once a program counter stores the address for the instruction to be repeated, it remains unchanged until the...
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